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1. 发明授权

US08384466B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08384466B2
公开(公告)日：2013-02-26
申请号：US13417548
申请日：2012-03-12
申请人： Toshiaki Kawasaki , Yasuhiro Agata , Masanori Shirahama , Toshihiro Kougami , Katsuya Arai
发明人： Toshiaki Kawasaki , Yasuhiro Agata , Masanori Shirahama , Toshihiro Kougami , Katsuya Arai
IPC分类号： H01H37/76
CPC分类号： H01L27/0207 , G11C17/18 , H01L23/5256 , H01L27/0288 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.
摘要翻译：半导体器件包括电熔丝电路和程序保护电路。电熔丝电路包括串联连接在一起的一个熔丝元件和一个晶体管，并放置在一个程序电源和一个接地之间，以及控制部分。程序保护电路与电熔丝电路并联在程序电源和接地之间。当在程序电源和接地之间施加浪涌电压时，上述结构允许一部分浪涌电流可以流过程序保护电路。

2. 发明授权

US07884642B2 System LSI 有权
标题翻译：系统LSI
公开(公告)号：US07884642B2
公开(公告)日：2011-02-08
申请号：US12722317
申请日：2010-03-11
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译：系统LSI包括输入/输出部分和逻辑电路部分。输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供来自I / O电源单元的源电源。逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。

3. 发明授权

US07764108B2 Electrical fuse circuit 有权
标题翻译：电熔丝电路
公开(公告)号：US07764108B2
公开(公告)日：2010-07-27
申请号：US11976672
申请日：2007-10-26
申请人： Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Shinichi Sumi , Yasue Yamamoto
发明人： Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Shinichi Sumi , Yasue Yamamoto
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L24/05 , H01L27/0629 , H01L2224/48091 , H01L2924/13091 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when an LSI power source is turned ON/OFF can be prevented.
摘要翻译：连接到串联熔丝器件的MOS晶体管的栅极由连接到与熔丝器件连接的相同电源的AND电路控制，从而将AND电路的一个输入端拉到地。因此，可以防止当LSI电源接通/断开时熔丝装置的错编程。

4. 发明授权

US07755941B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07755941B2
公开(公告)日：2010-07-13
申请号：US11971334
申请日：2008-01-09
申请人： Yasue Yamamoto , Masanori Shirahama , Yasuhiro Agata , Toshiaki Kawasaki
发明人： Yasue Yamamoto , Masanori Shirahama , Yasuhiro Agata , Toshiaki Kawasaki
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.
摘要翻译：在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

5. 发明授权

US07696779B2 System LSI 有权
标题翻译：系统LSI
公开(公告)号：US07696779B2
公开(公告)日：2010-04-13
申请号：US11526816
申请日：2006-09-26
申请人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro Agata , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译：系统LSI包括输入/输出部分和逻辑电路部分。输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供来自I / O电源单元的源电源。逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。

6. 发明申请

US20070058411A1 Semiconductor storage device including electrical fuse module 有权
标题翻译：半导体存储装置包括电熔丝模块
公开(公告)号：US20070058411A1
公开(公告)日：2007-03-15
申请号：US11501039
申请日：2006-08-09
申请人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
发明人： Shinichi Sumi , Hirohito Kikukawa , Yasuhiro Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara , Yasue Yamamoto
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027 , G11C29/785 , G11C2229/763
摘要： Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.
摘要翻译：提供多级的电熔丝块（100），每个级包括多个电熔丝芯（101）。电熔丝块（100）包括由移位寄存器（107）构成的程序移位寄存器块（103），它们被设置用于相应的电熔丝芯（101），顺序发送编程使能信号FPGI，并输出编程使能信号 FPGI连接到电熔丝芯（101）的NMOS晶体管（105）。当根据编程判定信号PBn执行编程时，程序移位寄存器块（103）发送程序使能信号FPGI。当不执行编程时，程序移位寄存器块（103）跳过编程使能信号FPGI。

7. 发明申请

US20060083046A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060083046A1
公开(公告)日：2006-04-20
申请号：US11245075
申请日：2005-10-07
申请人： Masashi Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara
发明人： Masashi Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.
摘要翻译：熔丝器件和程序晶体管彼此串联连接。触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化保险丝装置和程序晶体管的点。触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。

8. 发明授权

US07002865B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07002865B2
公开(公告)日：2006-02-21
申请号：US10935278
申请日：2004-09-08
申请人： Masashi Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara
发明人： Masashi Agata , Masanori Shirahama , Toshiaki Kawasaki , Ryuji Nishihara
IPC分类号： G11C7/02
CPC分类号： G11C16/0425
摘要： A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.
摘要翻译：非易失性半导体存储器件包括：第一位单元，包括其源极和漏极连接以形成第一控制栅极的第一MOS晶体管和具有与第一MOS晶体管共同的浮动栅极的第二MOS晶体管; 第二位单元，包括其源极和漏极连接以形成第二控制栅极的第三MOS晶体管和具有与第三MOS晶体管共同的浮置栅极的第四MOS晶体管; 以及差分放大器，其从相应的第二和第四MOS晶体管的漏极接收输入信号。

9. 发明授权

US06995436B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06995436B2
公开(公告)日：2006-02-07
申请号：US10860112
申请日：2004-06-04
申请人： Toshiaki Kawasaki
发明人： Toshiaki Kawasaki
IPC分类号： H01L29/76
CPC分类号： G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11558 , Y10S257/909
摘要： In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged in the column direction to constitute a sub array, and the sub arrays arranged in the column direction are arranged in parallel or axisymmetically in the row direction. With this arrangement, the substrate contact region, the well contact region, and the diffusion region of the PMOS transistor can be shared between the adjacent memory cells, thereby reducing the area of the cell array.
摘要翻译：在存储单元中，NMOS晶体管的衬底接触区域和PMOS晶体管的阱接触区域垂直于浮置栅极布置。在单元阵列中，存储单元和相对于存储单元轴对称布置的另一个存储单元在列方向上交替布置以构成子阵列，并且沿列方向排列的子阵列平行或轴对称地布置在行方向。利用这种布置，可以在相邻的存储单元之间共享衬底接触区域，阱接触区域和PMOS晶体管的扩散区域，从而减小单元阵列的面积。

10. 外观设计

USD351716S Shoe sole 失效
公开(公告)号：USD351716S
公开(公告)日：1994-10-25
申请号：US10862
申请日：1993-06-25
申请人： Toshiaki Kawasaki
设计人： Toshiaki Kawasaki

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