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1. 发明申请

US20120206970A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20120206970A1
公开(公告)日：2012-08-16
申请号：US13285181
申请日：2011-10-31
申请人： Toshifumi WATANABE , Hidetoshi Saito
发明人： Toshifumi WATANABE , Hidetoshi Saito
IPC分类号： G11C16/04
CPC分类号： G11C7/222 , G11C16/10 , G11C16/32
摘要： According to one embodiment, an interface includes first to third input circuits, delay and selection circuits. The first input circuit outputs an active first internal signal in response to an active first control signal received by a memory device. The second input circuit outputs an active second internal signal in response to an active second control signal received by the device while the device is receiving the active first control signal. The delay circuit outputs a selection signal in first or second states after the elapse of a first period from inactivation or activation of the first control signal. The selection circuit outputs the first and second internal signals as an enable signal while receiving the selection signal of the first and second states. The third input circuit outputs an input signal received from the outside from the interface to inside the device while receiving the active enable signal.
摘要翻译：根据一个实施例，接口包括第一至第三输入电路，延迟和选择电路。第一输入电路响应于由存储器件接收到的有效的第一控制信号而输出有效的第一内部信号。第二输入电路响应于设备在接收到有效的第一控制信号时接收到的有效的第二控制信号而输出有效的第二内部信号。延迟电路在从第一控制信号的失活或激活开始经过第一周期之后，输出第一或第二状态的选择信号。选择电路在接收第一和第二状态的选择信号的同时，将第一和第二内部信号作为使能信号输出。第三输入电路在接收到有效使能信号的同时，将从外部接收的输入信号输出到设备内部。

2. 发明授权

US08189424B2 Semiconductor memory device having plurality of types of memories integrated on one chip 有权
标题翻译：具有集成在一个芯片上的多种类型的存储器的半导体存储器件
公开(公告)号：US08189424B2
公开(公告)日：2012-05-29
申请号：US12397711
申请日：2009-03-04
申请人： Kazuto Uehara , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
发明人： Kazuto Uehara , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
IPC分类号： G11C8/00
CPC分类号： G11C7/1027 , G11C7/1006 , G11C7/1039 , G11C11/005 , G11C2029/0411
摘要： A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.
摘要翻译：配置为执行时钟同步突发读取操作的半导体存储器件包括具有不同库结构的多个缓冲存储器，以及存储从多个缓冲存储器读取的读取数据的第一和第二数据锁存电路。半导体存储装置还包括控制电路，其根据缓冲器的存储体结构，在时钟同步脉冲串读取操作时控制开始计数上升地址的定时和在第一数据锁存电路中存储读取数据的定时存储器作为读操作目标。

3. 发明申请

US20110013472A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110013472A1
公开(公告)日：2011-01-20
申请号：US12836851
申请日：2010-07-15
申请人： Tomoyuki HAMANO , Shigefumi Ishiguro , Toshifumi Watanabe , Kazuto Uehara
发明人： Tomoyuki HAMANO , Shigefumi Ishiguro , Toshifumi Watanabe , Kazuto Uehara
IPC分类号： G11C8/00 , G11C8/04
CPC分类号： G11C8/04 , G11C11/41 , G11C2029/0411
摘要： According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列，地址计数器，地址检测电路和控制电路。存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。地址计数器与时钟同步地增加包括行地址和列地址的地址，以顺序输出递增的地址。地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址，以输出检测信号。控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。

4. 发明申请

US20090316494A1 SEMICONDUCTOR MEMORY DEVICE HAVING PLURALITY OF TYPES OF MEMORIES INTEGRATED ON ONE CHIP 有权
标题翻译：具有集成在一个芯片上的多种类型的记忆体的半导体存储器件
公开(公告)号：US20090316494A1
公开(公告)日：2009-12-24
申请号：US12397711
申请日：2009-03-04
申请人： Kazuto UEHARA , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
发明人： Kazuto UEHARA , Toshifumi Watanabe , Shigefumi Ishiguro , Kazuyoshi Muraoka
IPC分类号： G11C7/10 , G11C8/18 , G11C7/00
CPC分类号： G11C7/1027 , G11C7/1006 , G11C7/1039 , G11C11/005 , G11C2029/0411
摘要： A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.
摘要翻译：配置为执行时钟同步突发读取操作的半导体存储器件包括具有不同库结构的多个缓冲存储器，以及存储从多个缓冲存储器读取的读取数据的第一和第二数据锁存电路。半导体存储装置还包括控制电路，其根据缓冲器的存储体结构，在时钟同步脉冲串读取操作时控制开始计数上升地址的定时和在第一数据锁存电路中存储读取数据的定时存储器作为读操作目标。

5. 发明授权

US07577058B2 Semiconductor device having input detection circuit which operates in a synchronous operation and an asynchronous operation 失效
标题翻译：具有输入检测电路的半导体器件，其在同步操作和异步操作中工作
公开(公告)号：US07577058B2
公开(公告)日：2009-08-18
申请号：US11774919
申请日：2007-07-09
申请人： Toshifumi Watanabe , Shigefumi Ishiguro
发明人： Toshifumi Watanabe , Shigefumi Ishiguro
IPC分类号： G11C8/00
CPC分类号： H03K19/017509 , H03K5/19
摘要： A semiconductor device includes a first input terminal, the first input terminal being supplied with an input signal, an input detection circuit including a delay circuit having a second input terminal and an output terminal, the input detection circuit detecting a shift in the input signal and generating a first pulse signal in response to the shift, the input detection circuit being connected to the first input terminal, and a control circuit for generating control signals, each of the control signals being generated in response to a synchronous operation or an asynchronous operation respectively.
摘要翻译：一种半导体器件，包括：第一输入端子，第一输入端子被提供有输入信号;输入检测电路，包括具有第二输入端子和输出端子的延迟电路;输入检测电路检测输入信号的偏移;以及响应于偏移产生第一脉冲信号，输入检测电路连接到第一输入端子，以及用于产生控制信号的控制电路，每个控制信号分别响应于同步操作或异步操作产生。

6. 发明授权

US06522122B2 Jitter measuring device and method 有权
标题翻译：抖动测量装置及方法
公开(公告)号：US06522122B2
公开(公告)日：2003-02-18
申请号：US09774196
申请日：2001-01-29
申请人： Toshifumi Watanabe , Akihiko Ando , Yuichi Miyaji
发明人： Toshifumi Watanabe , Akihiko Ando , Yuichi Miyaji
IPC分类号： G01R2312
CPC分类号： G01R31/31709 , G01R29/26 , H03L7/091 , H04L1/205
摘要： A signal to be measured is waveform-formatted to a square waveform that retains the frequency, duty ratio and jitter component of the original signal, and the leading (or trailing) edge of the waveform-formatted output is sampled by a sampling clock of a frequency slightly different from 1/N of the frequency fM of the signal to be measured. The samples are converted by an A/D converter to digital data Vn(t), which is stored in a memory. The difference between the stored digital data Vn(t) and the rise-up characteristic line V′(t) is calculated to detect jitter J′n(t).
摘要翻译：要测量的信号被波形格式化为保持原始信号的频率，占空比和抖动分量的方波，波形格式输出的前沿（或后沿）由采样时钟采样频率略微不同于要测量的信号的频率fM的1 / N。样本由A / D转换器转换成存储在存储器中的数字数据Vn（t）。计算存储的数字数据Vn（t）与上升特性线V'（t）之间的差异以检测抖动J'n（t）。

7. 发明授权

US5716971A Pyridine derivatives, their production and use 失效
标题翻译：吡啶衍生物，其生产和使用
公开(公告)号：US5716971A
公开(公告)日：1998-02-10
申请号：US694834
申请日：1996-08-09
申请人： Mitsuru Shiraishi , Toshifumi Watanabe
发明人： Mitsuru Shiraishi , Toshifumi Watanabe
IPC分类号： C07D213/50 , C07D213/53 , C07D213/63 , C07D213/79 , C07D213/84 , C07D213/89
CPC分类号： C07D213/53 , C07D213/50
摘要： Pyridine derivatives of the formula ##STR1## wherein the ring A stands for an optionally further substituted benzene ring; the ring B stands for an optionally substituted pyridine ring; Q stands for hydroxyl group, or OQ.sup.1 or Q.sup.1 wherein Q.sup.1 stands for an optionally substituted aliphatic hydrocarbon group; and n denotes 0 or 1, or their salts, which have potassium.channel opening activity and are useful as therapeutic agents of circulatory diseases such as angina pectoris, hypertension, etc.
摘要翻译：式IMA的吡啶衍生物，其中环A代表任选进一步取代的苯环; 环B代表任选取代的吡啶环; Q表示羟基或OQ1或Q1，其中Q1表示任选取代的脂族烃基; n表示0或1，或其盐，其具有钾通道开放活性，并且可用作循环系统疾病如心绞痛，高血压等的治疗剂。

8. 发明授权

US5694223A Digital image forming apparatus which specifies a sensitivity characteristic of a photoconductor 失效
标题翻译：指定光电导体的灵敏度特性的数字图像形成装置
公开(公告)号：US5694223A
公开(公告)日：1997-12-02
申请号：US611718
申请日：1996-03-06
申请人： Kentaro Katori , Toshifumi Watanabe , Yukihiko Okuno , Masaki Tanaka , Hironobu Nakata , Katsuyuki Hirata
发明人： Kentaro Katori , Toshifumi Watanabe , Yukihiko Okuno , Masaki Tanaka , Hironobu Nakata , Katsuyuki Hirata
IPC分类号： G03G15/00 , H04N1/407 , H04N1/00 , G03F3/08 , G03G21/00 , H04N1/46
CPC分类号： G03G15/5041 , G03G15/5037 , H04N1/407 , G03G2215/00042
摘要： A printer control unit carries out a predetermined calculation based on the amount of adhering toner detected by an AIDC sensor and the surface potential of a photoconductor detected by a V sensor to correct the light emission intensity of a light source to prepare light emission characteristic data for .gamma. correction to obtain an optimal image. A .gamma. correcting unit corrects an image signal output from an image signal processing unit using the calculated light emission characteristic data for .gamma. correction to control the light source to emit light based on the corrected data. More specifically, since the .gamma. correction data is obtained by calculation, optimal .gamma. correction can always be carried out without a memory of a large capacity.
摘要翻译：打印机控制单元基于由AIDC传感器检测到的附着调色剂的量和由V传感器检测的感光体的表面电位进行预定的计算，以校正光源的发光强度，以准备用于伽马校正以获得最佳图像。伽马校正单元使用所计算的用于伽马校正的发光特性数据来校正从图像信号处理单元输出的图像信号，以基于校正数据控制光源发光。更具体地，由于通过计算获得伽马校正数据，所以可以总是在没有大容量的存储器的情况下执行最佳伽马校正。

9. 发明授权

US5581221A Electrophotographic image forming apparatus 失效
标题翻译：电子照相成像设备
公开(公告)号：US5581221A
公开(公告)日：1996-12-03
申请号：US354808
申请日：1994-12-13
申请人： Atsushi Kawai , Hiroshi Sakakibara , Toshifumi Watanabe , Tetsuya Sakai , Hiroshi Nishikawa
发明人： Atsushi Kawai , Hiroshi Sakakibara , Toshifumi Watanabe , Tetsuya Sakai , Hiroshi Nishikawa
IPC分类号： G03G15/00 , G03G15/08 , G03G21/00
CPC分类号： G03G15/5041 , G03G15/0853 , G03G15/0855 , G03G2215/00042
摘要： A copying machine wherein a developing device is provided with a first sensor for detecting the toner density in a developer and a second sensor which is provided around a photosensitive drum for detecting the amount of deposited toner on a test pattern. The toner supply is controlled according to a result detected by the second sensor. When the toner density is judged high from a result detected by the first sensor, a developing bias voltage is set high by a computer, and when the toner density is judged low, the developing bias voltage is set low.
摘要翻译：一种复印机，其中显影装置设置有用于检测显影剂中的调色剂浓度的第一传感器和设置在感光鼓周围的第二传感器，用于检测测试图案上沉积的调色剂的量。根据第二传感器检测到的结果控制调色剂供应。当从第一传感器检测到的结果判断为高浓度的调色剂浓度时，通过计算机将显影偏压设置得高，并且当调色剂浓度判定为低时，显影偏压被设定为低。

10. 发明授权

US5270308A 1,3-benzoxazine derivatives, their production and use 失效
标题翻译： 1,3-苯并恶嗪衍生物，其生产和使用
公开(公告)号：US5270308A
公开(公告)日：1993-12-14
申请号：US764692
申请日：1991-09-25
申请人： Mitsuru Shiraishi , Shohei Hashiguchi , Toshifumi Watanabe
发明人： Mitsuru Shiraishi , Shohei Hashiguchi , Toshifumi Watanabe
IPC分类号： C07D265/16 , C07D413/04 , C07D417/04 , C07F7/08 , A61K31/535 , C07D265/12 , C07D498/04
CPC分类号： C07D413/04 , C07D265/16 , C07D417/04 , C07F7/0812
摘要： A new compound of the formula: ##STR1## wherein ##STR2## is an optionally substituted benzene ring; R.sup.1 is a carbocyclic or heterocyclic group which is linked to the 4-position of the 1,3-benzoxazine ring through a carbon-carbon bond, a hydrocarbon residue, etc.; and R.sup.2 and R.sup.3 are independently a hydrogen atom or an optionally substituted C.sub.1-6 alkyl group, etc., or a salt thereof is useful for treating and preventing heart, circulatory, respiratory and cerebral diseases.

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