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1. 发明申请

US20220310450A1 STACKED SEMICONDUCTOR, WAFER STACK, METHOD OF MANUFACTURING STACKED SEMICONDUCTOR, ASSISTANCE DEVICE, AND PROGRAM 有权
公开(公告)号：US20220310450A1
公开(公告)日：2022-09-29
申请号：US17765997
申请日：2019-10-09
申请人： UltraMemory Inc.
发明人： Kazuhiko KAJIGAYA
IPC分类号： H01L21/8239 , H01L25/065 , H01L27/108
摘要： Provided are: a laminated semiconductor which enables curbing of manufacturing cost; a wafer laminate; a method for manufacturing the laminated semiconductor; an assistance device; and a program. This laminated semiconductor formed by laminating a plurality of chips is provided with: a logic chip; and a memory part that is stacked on the logic chip and has at least one memory chip communicable with the logic chip. The memory chip has: at least two memory bodies that have memory circuits and that are arranged side by side in a direction intersecting the stacking direction; and a connection part which is provided with a prescribed width between the memory bodies and which connects the memory bodies arranged side by side.

2. 发明授权

US11437350B2 Semiconductor device 有权
公开(公告)号：US11437350B2
公开(公告)日：2022-09-06
申请号：US17158774
申请日：2021-01-26
申请人： UltraMemory Inc.
发明人： Naoki Ogawa , Toshitugu Ueda , Kazuo Yamaguchi
IPC分类号： G11C16/04 , H01L25/065 , H01L25/18 , H01L25/07 , H01L23/48 , H01L49/02 , H04B5/00 , G11C5/06 , H04B5/02 , H01L23/498 , H01L23/64 , H01L27/108 , G11C5/02
摘要： A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil. The semiconductor device is also provided with an interposer, which is disposed on one end in the laminating direction of the memory chips, and which has, for each of the memory chips: a second transmission/reception coil coupled to the first transmission/reception coil by means of inductive coupling; second lead-out lines led out from both ends of the second transmission/reception coil; and a second transmission/reception circuit, which is connected to the second lead-out lines, and which inputs/outputs signals to/from the second transmission/reception coil.

3. 发明授权

US10861530B2 Semiconductor storage device 有权
公开(公告)号：US10861530B2
公开(公告)日：2020-12-08
申请号：US16090716
申请日：2016-04-08
申请人： ULTRAMEMORY INC.
发明人： Yasutoshi Yamada , Ryuji Takishita
IPC分类号： G11C11/406 , G11C11/408
摘要： The purpose of the present invention is to achieve a system for solving a row hammer issue without significantly increasing a DRAM chip area. A semiconductor storage device comprises: a memory unit including a plurality of memory cells; an address latch unit that receives an active command and an address therefor, and latches and holds the address every time the active command is received; a refresh control unit that, when receiving a refresh command, instructs a memory access control unit to carry out a regular refresh operation while instructing the memory access control unit to carry out an interrupt refresh operation for an address near the address latched by the address latch unit; and the memory access control unit that carries out the regular refresh operation and the interrupt refresh operation for the memory unit on the basis of the instruction from the refresh control unit.

4. 发明申请

US20200043899A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200043899A1
公开(公告)日：2020-02-06
申请号：US16595979
申请日：2019-10-08
申请人： UltraMemory Inc.
发明人： Naoki Ogawa , Toshitugu Ueda , Kazuo Yamaguchi
IPC分类号： H01L25/065 , H01L25/18 , H01L25/07 , H01L23/48 , H01L49/02 , H04B5/00 , H04B5/02 , H01L23/498 , H01L23/64 , H01L27/108
摘要： A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil. The semiconductor device is also provided with an interposer, which is disposed on one end in the laminating direction of the memory chips, and which has, for each of the memory chips: a second transmission/reception coil coupled to the first transmission/reception coil by means of inductive coupling; second lead-out lines led out from both ends of the second transmission/reception coil; and a second transmission/reception circuit, which is connected to the second lead-out lines, and which inputs/outputs signals to/from the second transmission/reception coil.

5. 发明申请

US20220223531A1 SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFOR 有权
公开(公告)号：US20220223531A1
公开(公告)日：2022-07-14
申请号：US17615047
申请日：2019-05-31
申请人： ULTRAMEMORY INC.
发明人： Takatoshi MASUDA , Fumitake OKUTSU
IPC分类号： H01L23/538 , H01L25/065 , H01L21/48 , H01L25/00
摘要： A semiconductor module that can absorb thermal stress, and a manufacturing method therefor are provided. A semiconductor module includes a film interposer that includes a plurality of through electrodes which run in the thickness direction; a logic chip that is disposed on one surface side of the film interposer, and is connected electrically to the through electrodes; and a RAM unit that is a RAM module disposed on the other surface side of the film interposer, and connected electrically to the logic chip via the through electrodes.

6. 发明申请

US20210151415A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20210151415A1
公开(公告)日：2021-05-20
申请号：US17158774
申请日：2021-01-26
申请人： UltraMemory Inc.
发明人： Naoki OGAWA , Toshitugu UEDA , Kazuo YAMAGUCHI
IPC分类号： H01L25/065 , H01L25/18 , H01L25/07 , H01L23/48 , H01L49/02 , H04B5/00 , H04B5/02 , H01L23/498 , H01L23/64 , H01L27/108
摘要： A semiconductor device includes a plurality of memory chips laminated to each other, each of the memory chips include a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil. The semiconductor device is also provided with an interposer, which is disposed on one end in the laminating direction of the memory chips, and which has, for each of the memory chips: a second transmission/reception coil coupled to the first transmission/reception coil by means of inductive coupling; second lead-out lines led out from both ends of the second transmission/reception coil; and a second transmission/reception circuit, which is connected to the second lead-out lines, and which inputs/outputs signals to/from the second transmission/reception coil.

7. 发明申请

US20210018952A1 SEMICONDUCTOR MODULE 有权
公开(公告)号：US20210018952A1
公开(公告)日：2021-01-21
申请号：US16618508
申请日：2017-06-02
申请人： UltraMemory Inc.
发明人： Kazuhiko KAJIGAYA , Takao ADACHI
IPC分类号： G06F1/02
摘要： Provided is a semiconductor module which enables a memory bandwidth to be widened, and which enables data transfer efficiency to be improved by reducing power consumption. A semiconductor module 1 comprises: an interposer 10; and a processing unit 20 which has a plurality of processing unit main bodies 21 arrayed to be side by side with each other in a first direction F1 along the plate surface of the interposer 10, and which is placed on the interposer 10 so as to be electrically connected to the interposer 10. The processing unit main bodies 21 are provided with a plurality of subset units 22 each including: one arithmetic unit 23 including at least one core 25; and one memory unit 24 that is configured from a stacked-type RAM module and that is disposed to be side by side with the calculation unit 23 in the first direction F1. The plurality of subset units 22 are arrayed to be side by side with each other in a second direction F2 that intersects with the first direction F1.

8. 发明申请

US20200286546A1 SUB-AMPLIFIER, SWITCHING DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200286546A1
公开(公告)日：2020-09-10
申请号：US16645640
申请日：2017-09-11
申请人： UltraMemory Inc.
发明人： Yasutoshi YAMADA
IPC分类号： G11C11/4091 , G11C7/06
摘要： Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplifier SAP comprises: a first pre-charge circuit 110 that releases pre-charges of a pair of local wires LIOT/LIOB; a local inversion drive circuit 120 that, on the basis of a write signal WT, inverts and transfers write data to a sense amplifier SA from a main wire MIOB via one of the local wires LIOT/LIOB; a local non-inversion drive circuit 130 that, on the basis of the write signal WT, transfers the write data to the sense amplifier SA from the main wire MIOB via the other one of the local wires LIOT/LIOB; and a main inversion drive circuit 140 that, on the basis of a read signal RT, inverts and transfers read data to the main wire MIOB from one of the local wires LIOT/LIOB.

9. 发明授权

US10741525B2 Semiconductor module 有权
公开(公告)号：US10741525B2
公开(公告)日：2020-08-11
申请号：US16618765
申请日：2017-06-02
申请人： UltraMemory Inc.
发明人： Ryuji Takishita , Takao Adachi
IPC分类号： H01L25/065 , H01L23/498 , H01L23/00 , H01L23/367 , H01L25/07 , H01L25/11 , H01L27/02
摘要： The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

10. 发明授权

US11183484B2 Semiconductor module, DIMM module, manufacturing method of semiconductor module, and manufacturing method of DIMM module 有权
公开(公告)号：US11183484B2
公开(公告)日：2021-11-23
申请号：US16962312
申请日：2019-11-11
申请人： ULTRAMEMORY INC.
发明人： Fumitake Okutsu , Takao Adachi
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor module 1 having a plurality of memory chips 21 includes: a memory substrate 10 having a power supply circuit 12 exposed on an arrangement surface as one surface of the memory substrate 10; and at least one memory unit 20 arranged over the arrangement surface of the memory substrate 10. The memory unit 20 includes: the plurality of memory chips 21 stacked together such that a stacking direction D is along the arrangement surface; a through electrode 22 passing through the plurality of memory chips 21 in the stacking direction D; and an electrode layer 23 formed on one end surface in the stacking direction D and connected to the through electrode 22 and the power supply circuit 12.

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