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1. 发明授权

US10741525B2 Semiconductor module 有权
公开(公告)号：US10741525B2
公开(公告)日：2020-08-11
申请号：US16618765
申请日：2017-06-02
申请人： UltraMemory Inc.
发明人： Ryuji Takishita , Takao Adachi
IPC分类号： H01L25/065 , H01L23/498 , H01L23/00 , H01L23/367 , H01L25/07 , H01L25/11 , H01L27/02
摘要： The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

2. 发明授权

US11183484B2 Semiconductor module, DIMM module, manufacturing method of semiconductor module, and manufacturing method of DIMM module 有权
公开(公告)号：US11183484B2
公开(公告)日：2021-11-23
申请号：US16962312
申请日：2019-11-11
申请人： ULTRAMEMORY INC.
发明人： Fumitake Okutsu , Takao Adachi
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor module 1 having a plurality of memory chips 21 includes: a memory substrate 10 having a power supply circuit 12 exposed on an arrangement surface as one surface of the memory substrate 10; and at least one memory unit 20 arranged over the arrangement surface of the memory substrate 10. The memory unit 20 includes: the plurality of memory chips 21 stacked together such that a stacking direction D is along the arrangement surface; a through electrode 22 passing through the plurality of memory chips 21 in the stacking direction D; and an electrode layer 23 formed on one end surface in the stacking direction D and connected to the through electrode 22 and the power supply circuit 12.

3. 发明授权

US10529385B2 Layered semiconductor device, and production method therefor 有权
公开(公告)号：US10529385B2
公开(公告)日：2020-01-07
申请号：US16070738
申请日：2016-12-22
申请人： ULTRAMEMORY INC.
发明人： Yasutoshi Yamada , Kouji Uemura , Takao Adachi
IPC分类号： G11C5/14 , G11C29/04 , G11C11/407 , H01L25/065 , H01L25/07
摘要： A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

4. 发明授权

US10269734B2 Semiconductor element 有权
公开(公告)号：US10269734B2
公开(公告)日：2019-04-23
申请号：US15741690
申请日：2015-07-16
申请人： ULTRAMEMORY INC.
发明人： Motoaki Saito , Takao Adachi
IPC分类号： H01L23/66 , H01L21/822 , H01L27/04 , H01L21/768
摘要： A semiconductor element that has an element first main surface, an element second main surface that is the reverse surface from the element first main surface, and an element side surface. The semiconductor element is configured from a semiconductor substrate part and an insulating layer part and is provided with: a signal transmission/reception terminal that is provided to the element first main surface and that contacts and can transmit/receive signals to/from an external-substrate signal transmission/reception terminal that is provided to an external substrate that is external to the semiconductor element; and a signal transmission/reception coil that is provided to the element side surface and that, via the element side surface, can transmit/receive signals in a non-contact manner to/from an external-semiconductor-element signal transmission/reception part that is provided to an external semiconductor element that is external to the semiconductor element. The signal transmission/reception coil has: a conductor that is formed inside the insulating layer part; and a conductor that is formed inside the semiconductor substrate part.

5. 发明授权

US11410970B2 Semiconductor module 有权
公开(公告)号：US11410970B2
公开(公告)日：2022-08-09
申请号：US16913524
申请日：2020-06-26
申请人： UltraMemory Inc.
发明人： Ryuji Takishita , Takao Adachi
IPC分类号： H01L25/065 , H01L23/367 , H01L23/498 , H01L23/00 , H01L25/04 , H01L25/07 , H01L25/11 , H01L27/02
摘要： The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

6. 发明授权

US10714151B2 Layered semiconductor device, and production method therefor 有权
公开(公告)号：US10714151B2
公开(公告)日：2020-07-14
申请号：US16694136
申请日：2019-11-25
申请人： ULTRAMEMORY INC.
发明人： Yasutoshi Yamada , Kouji Uemura , Takao Adachi
IPC分类号： G11C5/14 , G11C29/04 , G11C11/407 , H01L25/065 , H01L25/07 , G11C5/00 , H01L25/18 , G11C29/00 , G11C29/44 , G11C7/12 , G11C29/12 , G11C8/08
摘要： The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.

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