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    • 5. 发明授权
    • Sealing system for rotating component of a pump
    • 泵的旋转部件密封系统
    • US6129533A
    • 2000-10-10
    • US272167
    • 1999-03-18
    • Jens-Uwe BrandtGerhard RohlfingVejen Hristov
    • Jens-Uwe BrandtGerhard RohlfingVejen Hristov
    • F04C2/16F04C15/00F16J15/32F04C2/00
    • F04C15/0038
    • The invention relates to a fluid-conveying machine, in particular, a pump having a component rotating in a stationary housing part inside an annular gap. The stationary housing part separates an interior having a higher product pressure from an exterior having a lower pressure. A rotating component is mounted in an external bearing which is sealed with respect to the interior via a sealing system. In order to improve the sealing, the invention provides that the annular gap is formed between two sliding bearing shells which comprise extremely hard, wear-resistant materials and, in accordance with the operating principle of a radial sliding bearing, form a first pressure-reducing stage. A feedback device, which feeds back the leakage from this first sealing stage into the conveying process of the machine, is connected downstream of the first pressure-reducing stage. A second sealing stage is arranged axially downstream of the feedback device. The second sealing stage may be constructed as a simple seal, such as a lip seal and/or a simple end face seal.
    • 本发明涉及一种流体输送机,特别是具有在环形间隙内的固定壳体部分中旋转的部件的泵。 固定壳体部分将具有较高产品压力的内部与具有较低压力的外部分离。 旋转部件安装在通过密封系统相对于内部密封的外部轴承中。 为了改善密封性,本发明提供了环形间隙形成在包括极硬耐磨材料的两个滑动轴承壳之间,并且根据径向滑动轴承的工作原理形成第一减压 阶段。 反馈装置将从第一密封阶段的泄漏反馈到机器的输送过程中,连接在第一减压级的下游。 第二密封台被布置在反馈装置的轴向下游。 第二密封阶段可以构造成简单的密封,例如唇形密封和/或简单的端面密封。
    • 6. 发明授权
    • Test interface for memory elements
    • 测试界面的内存元素
    • US07844871B2
    • 2010-11-30
    • US12268903
    • 2008-11-11
    • Uwe BrandtStefan BuettnerWerner JuchmesJuergen Pille
    • Uwe BrandtStefan BuettnerWerner JuchmesJuergen Pille
    • G01R31/28
    • G11C29/16G11C29/32G11C2029/3202
    • A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
    • 一种用于测试具有内置于自检(ABIST)中的阵列的集成电路的存储器元件的方法,包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口,提供多路复用(MUX)级 邻近每个锁存器的扫描输入端口,向锁存器的数据输入端口提供功能信号输入,通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器,将锁存器设置为ABIST模式,产生多个 的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行,确定是否执行了一个或多个测试模式,并通过停用ABIST使能来将锁存器设置为正常运行模式 信号。
    • 7. 发明申请
    • TEST INTERFACE FOR MEMORY ELEMENTS
    • 记忆元素的测试界面
    • US20100122128A1
    • 2010-05-13
    • US12268903
    • 2008-11-11
    • Uwe BrandtStefan BuettnerWerner JuchmesJuergen Pille
    • Uwe BrandtStefan BuettnerWerner JuchmesJuergen Pille
    • G11C29/12G06F11/27
    • G11C29/16G11C29/32G11C2029/3202
    • A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
    • 一种用于测试具有内置于自检(ABIST)中的阵列的集成电路的存储器元件的方法,包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口,提供多路复用(MUX)级 邻近每个锁存器的扫描输入端口,向锁存器的数据输入端口提供功能信号输入,通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器,将锁存器设置为ABIST模式,产生多个 的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行,确定是否执行了一个或多个测试模式,并通过停用ABIST使能来将锁存器设置为正常运行模式 信号。