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1. 发明授权

US07844871B2 Test interface for memory elements 失效
标题翻译：测试界面的内存元素
公开(公告)号：US07844871B2
公开(公告)日：2010-11-30
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

2. 发明申请

US20100122128A1 TEST INTERFACE FOR MEMORY ELEMENTS 失效
标题翻译：记忆元素的测试界面
公开(公告)号：US20100122128A1
公开(公告)日：2010-05-13
申请号：US12268903
申请日：2008-11-11
申请人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
发明人： Uwe Brandt , Stefan Buettner , Werner Juchmes , Juergen Pille
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/16 , G11C29/32 , G11C2029/3202
摘要： A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.
摘要翻译：一种用于测试具有内置于自检（ABIST）中的阵列的集成电路的存储器元件的方法，包括提供ABIST接口以在ABIST引擎和被测存储元件的多个锁存器之间进行接口，提供多路复用（MUX）级邻近每个锁存器的扫描输入端口，向锁存器的数据输入端口提供功能信号输入，通过激活ABIST使能信号并将ABIST使能信号传送到每个锁存器，将锁存器设置为ABIST模式，产生多个的ABIST测试信号与ABIST引擎并行地应用ABIST测试信号并且与锁存器的扫描输入端口并行，确定是否执行了一个或多个测试模式，并通过停用ABIST使能来将锁存器设置为正常运行模式信号。

3. 发明申请

US20130128684A1 REDUCED LEAKAGE BANKED WORDLINE HEADER 审中-公开
标题翻译：减少泄漏银行字头
公开(公告)号：US20130128684A1
公开(公告)日：2013-05-23
申请号：US13466973
申请日：2012-05-08
申请人： Stefan Buettner , Thomas Froehnel , Werner Juchmes , Rolf Sautter , Victor Zyuban
发明人： Stefan Buettner , Thomas Froehnel , Werner Juchmes , Rolf Sautter , Victor Zyuban
IPC分类号： G11C5/14 , G11C8/10
CPC分类号： G11C5/14 , G11C8/08 , G11C8/10
摘要： A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication.
摘要翻译：存储器阵列可以配置有头部装置以减少泄漏。标题装置与解码器耦合以接收存储器地址指示的至少第一部分，并被耦合以从电源接收电流。每个头部装置适于从电源向与存储器地址指示的第一部分指示的存储体相对应的一组字线驱动器提供电力。每个逻辑设备被耦合以从解码器接收存储器地址指示的至少第二部分。每个逻辑设备被耦合以激活与由存储器地址指示的第二部分指示的字线的字线驱动器耦合的字线驱动器。

4. 发明授权

US08422313B2 Reduced power consumption memory circuitry 失效
标题翻译：降低功耗记忆电路
公开(公告)号：US08422313B2
公开(公告)日：2013-04-16
申请号：US13284480
申请日：2011-10-28
申请人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
发明人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C29/846 , G11C2207/005
摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.
摘要翻译：在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。选择电路将全局位线分割成全局位线的上部和下部。选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。

5. 发明申请

US20120155188A1 REDUCED POWER CONSUMPTION MEMORY CIRCUITRY 失效
标题翻译：降低功耗记忆电路
公开(公告)号：US20120155188A1
公开(公告)日：2012-06-21
申请号：US13284480
申请日：2011-10-28
申请人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
发明人： Stefan Buettner , David A. Hrusecky , Werner Juchmes , Wolfgang Penth , Rolf Sautter
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C29/846 , G11C2207/005
摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.
摘要翻译：在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。选择电路将全局位线分割成全局位线的上部和下部。选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。

6. 发明授权

US07558138B1 Bypass circuit for memory arrays 失效
标题翻译：存储器阵列的旁路电路
公开(公告)号：US07558138B1
公开(公告)日：2009-07-07
申请号：US12242564
申请日：2008-09-30
申请人： Sebastian Ehrenreich , Werner Juchmes , Atnje Mueller , Silke Salewski
发明人： Sebastian Ehrenreich , Werner Juchmes , Atnje Mueller , Silke Salewski
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C29/1201 , G11C29/32 , G11C2029/1204 , G11C2029/3202
摘要： A method for bypassing a memory array in a circuit having a global bit line, a test port configured to output a logic test, a memory portion connected to the global bit line via a word line, a header device being connected to the global bit line via a pre-charge signal, the header device being configured to recharge the global bit line. A gating signal is sent to a gating device connected to the header device. The gating device is switched to a test mode upon receipt of the gating signal. The bypass data signal is sent to an evaluating device connected to the gating device, the evaluating device being configured to output a logic test. The logic test is output through the test port upon receipt of bypass data signal.
摘要翻译：一种用于绕过具有全局位线的电路中的存储器阵列的方法，被配置为输出逻辑测试的测试端口，经由字线连接到全局位线的存储器部分，连接到全局位线的标题设备通过预充电信号，头部设备被配置为对全局位线进行再充电。选通信号被发送到连接到报头装置的选通装置。门控装置在接收到门控信号时切换到测试模式。旁路数据信号被发送到连接到选通装置的评估装置，评估装置被配置为输出逻辑测试。接收到旁路数据信号后，逻辑测试通过测试端口输出。

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