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1. 发明授权

US08984320B2 Command paths, apparatuses and methods for providing a command to a data block 有权
标题翻译：用于向数据块提供命令的命令路径，装置和方法
公开(公告)号：US08984320B2
公开(公告)日：2015-03-17
申请号：US13074972
申请日：2011-03-29
申请人： Venkatraghavan Bringivijayaraghavan
发明人： Venkatraghavan Bringivijayaraghavan
IPC分类号： G06F1/12 , G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/109 , G11C7/1093
摘要： Command paths, apparatuses, and methods for providing a command to a data block are described. In an example command path, a command receiver is configured to receive a command and a command buffer is coupled to the command receiver and configured to receive the command and provide a buffered command. A command block is coupled to the command buffer to receive the buffered command. The command block is configured to provide the buffered command responsive to a clock signal and is further configured to add a delay before to the buffered command, the delay based at least in part on a shift count. A command tree is coupled to the command block to receive the buffered command and configured to distribute the buffered command to a data block.
摘要翻译：描述用于向数据块提供命令的命令路径，设备和方法。在示例命令路径中，命令接收器被配置为接收命令，并且命令缓冲器耦合到命令接收器并且被配置为接收命令并提供缓冲的命令。一个命令块连接到命令缓冲区以接收缓冲命令。命令块被配置为响应于时钟信号提供缓冲的命令，并且还被配置为在缓冲的命令之前添加延迟，所述延迟至少部分地基于移位计数。命令树耦合到命令块以接收缓冲命令并且被配置为将缓冲的命令分发到数据块。

2. 发明授权

US08797080B2 Circuits, apparatuses, and methods for delay models 有权
标题翻译：延迟模型的电路，装置和方法
公开(公告)号：US08797080B2
公开(公告)日：2014-08-05
申请号：US13619859
申请日：2012-09-14
申请人： Venkatraghavan Bringivijayaraghavan , Jason Brown , Tyler J. Gomm
发明人： Venkatraghavan Bringivijayaraghavan , Jason Brown , Tyler J. Gomm
IPC分类号： H03H11/26
CPC分类号： H03L7/0802 , G11C7/04 , G11C7/222 , H03K5/159 , H03L7/08 , H03L7/0816
摘要： Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.
摘要翻译：公开延迟模型的电路，装置和方法。在一个这样的示例电路中，第一延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第一输出信号。第二延迟模型电路被配置为通过对通过路径的信号的延迟进行建模来提供第二输出信号。比较电路耦合到第一和第二延迟模型电路。比较电路被配置为比较来自第一延迟模型电路的第三信号和来自第二延迟模型电路的第四信号，并且响应于提供调整信号以调整第二延迟模型电路的延迟。

3. 发明授权

US07245548B2 Techniques for reducing leakage current in memory devices 有权
标题翻译：降低存储器件泄漏电流的技术
公开(公告)号：US07245548B2
公开(公告)日：2007-07-17
申请号：US10900246
申请日：2004-07-27
申请人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
发明人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译：利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

4. 发明申请

US20060023542A1 Techniques for reducing leakage current in memory devices 有权
标题翻译：降低存储器件泄漏电流的技术
公开(公告)号：US20060023542A1
公开(公告)日：2006-02-02
申请号：US10900246
申请日：2004-07-27
申请人： Scott Derner , Venkatraghavan Bringivijayaraghavan , Abhay Dixit , Scot Graham , Stephen Porter , Ethan Williford
发明人： Scott Derner , Venkatraghavan Bringivijayaraghavan , Abhay Dixit , Scot Graham , Stephen Porter , Ethan Williford
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译：利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

5. 发明授权

US09157960B2 Through-substrate via (TSV) testing 有权
标题翻译：通过基板通孔（TSV）测试
公开(公告)号：US09157960B2
公开(公告)日：2015-10-13
申请号：US13411167
申请日：2012-03-02
申请人： Venkatraghavan Bringivijayaraghavan , Jason M. Brown
发明人： Venkatraghavan Bringivijayaraghavan , Jason M. Brown
IPC分类号： G01R31/3185 , H01L21/66 , G01R31/317
CPC分类号： H01L22/22 , G01R31/31717 , G01R31/318513 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments, an apparatus is provided that includes a number of through-substrate vias to couple to one or more devices, at least one redundant through-substrate via to allow a repair of the apparatus, and a pair of pull-up devices coupled to the through-substrate vias and the redundant through-substrate via to provide a high-data value to the first end of the respective through-substrate vias. A test register is coupled the second end of each of the through-substrate vias and the redundant through-substrate via to store a received version of the high-data value. A comparator compares the high-data value with the received version of the high-data value to test the through-substrate vias for short-circuit connections.
摘要翻译：各种实施例包括用于在相互连接的骰子的堆叠中测试和修复穿过衬底通孔的装置和方法。在各种实施例中，提供了一种装置，其包括多个穿过基板通孔以耦合到一个或多个设备，至少一个冗余的通过基板通孔以允许修复该设备，以及一对上拉设备耦合通过衬底通孔和冗余通过衬底通孔，以提供相应贯穿衬底通孔的第一端的高数据值。测试寄存器耦合每个贯穿衬底通孔的第二端和冗余通过衬底通孔以存储高数据值的接收版本。比较器将高数据值与高数据值的接收版本进行比较，以测试用于短路连接的贯穿衬底通孔。

6. 发明授权

US08582380B2 Systems, circuits, and methods for charge sharing 有权
标题翻译：用于电荷共享的系统，电路和方法
公开(公告)号：US08582380B2
公开(公告)日：2013-11-12
申请号：US13333822
申请日：2011-12-21
申请人： Venkatraghavan Bringivijayaraghavan
发明人： Venkatraghavan Bringivijayaraghavan
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/1048
摘要： Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.
摘要翻译：公开了用于电荷共享的系统，电路和方法。在一个这样的示例系统中，第一线被配置为被驱动到表示要放置在第一线上的数据的第一电压，然后预充电到第一预充电电压。第二线被配置为被驱动到表示要放置在第二线上的数据的第二电压，然后预充电到第二预充电电压。电荷共享装置耦合在第一线和第二线之间。电荷共享装置被配置为在将第一和第二线路驱动到表示要放置在相应线路上的数据的相应第一和第二电压之后，选择性地允许来自第一线路的电荷流到第二线路。

7. 发明授权

US08441888B2 Write command and write data timing circuit and methods for timing the same 有权
标题翻译：写命令和写数据定时电路和定时方法相同
公开(公告)号：US08441888B2
公开(公告)日：2013-05-14
申请号：US13149435
申请日：2011-05-31
申请人： Venkatraghavan Bringivijayaraghavan , Jason Brown
发明人： Venkatraghavan Bringivijayaraghavan , Jason Brown
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/18 , G11C2207/2272
摘要： Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.
摘要翻译：用于锁存写命令的电路，存储器和方法，并且稍后提供包括写命令和写数据定时电路的写数据。一个这样的定时电路包括内部写入命令锁存器，以响应写入命令锁存信号来锁存内部写入命令。在延迟延迟之后，内部写命令锁存器响应于写命令锁存信号释放锁存的写命令。定时电路还包括写平均触发器（FF）电路和写数据寄存器。一种这样的方法包括产生和锁定内部写命令。锁存的内部写入命令在响应于存储器时钟信号的延迟延迟之后被释放。内部写入命令通过内部写命令路径进行传播。写数据被捕获，并且内部写命令响应于写时钟信号而被锁存。捕获的写入数据被释放以写入存储器。

8. 发明申请

US20120269015A1 COMMAND PATHS, APPARATUSES, MEMORIES, AND METHODS FOR PROVIDING INTERNAL COMMANDS TO A DATA PATH 有权
标题翻译：用于向数据路径提供内部命令的命令PATHS，设备，记忆和方法
公开(公告)号：US20120269015A1
公开(公告)日：2012-10-25
申请号：US13093640
申请日：2011-04-25
申请人： Venkatraghavan Bringivijayaraghavan
发明人： Venkatraghavan Bringivijayaraghavan
IPC分类号： G11C8/18 , H03L7/00
CPC分类号： G11C7/222 , G11C7/109 , G11C7/1093 , G11C7/22 , H03L7/00
摘要： Command paths, apparatuses, memories, and methods for providing an internal command to a data path are disclosed. In an example method, a command is received and propagated through a command path to provide an internal command. Further included in the method is determining a difference between a latency value and a path delay difference, the path delay difference representing a modeled path delay difference between the command path and the data path measured in terms of a number of clock periods. The propagation of the command through the command path to the data path is delayed by a delay based at least in part on the difference between the latency value and the path delay difference. The internal command is provided to the data path responsive to an internal clock signal.
摘要翻译：公开了用于向数据路径提供内部命令的命令路径，装置，存储器和方法。在一个示例方法中，通过命令路径接收和传播命令以提供内部命令。该方法还包括确定等待时间值和路径延迟差之间的差异，路径延迟差表示按照时钟周期数来测量的命令路径和数据路径之间的建模路径延迟差。命令通过命令路径传播到数据路径的延迟至少部分地基于延迟值和路径延迟差之间的差异延迟延迟。内部命令根据内部时钟信号提供给数据通路。

9. 发明授权

US07746720B2 Techniques for reducing leakage current in memory devices 有权
标题翻译：降低存储器件泄漏电流的技术
公开(公告)号：US07746720B2
公开(公告)日：2010-06-29
申请号：US11879396
申请日：2007-07-17
申请人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
发明人： Scott J. Derner , Venkatraghavan Bringivijayaraghavan , Abhay S. Dixit , Scot M. Graham , Stephen R. Porter , Ethan A. Williford
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C11/4085
摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
摘要翻译：利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

10. 发明授权

US06965263B2 Bulk node biasing method and apparatus 有权
标题翻译：批量节点偏置方法和装置
公开(公告)号：US06965263B2
公开(公告)日：2005-11-15
申请号：US10268313
申请日：2002-10-10
申请人： Venkatraghavan Bringivijayaraghavan
发明人： Venkatraghavan Bringivijayaraghavan
IPC分类号： H02M3/07 , H03K17/06 , G05F3/02
CPC分类号： H03K17/063 , H02M3/073 , H03K2217/0018
摘要： A biasing circuit with application to a charge pump environment for coupling the appropriate terminal voltage potentials to the bulk node. Specifically, a pass gate, such as a transistor of an integrated circuit, operates to isolate a boosted voltage input from a boosting device such as a charge pump voltage doubler and to transfer or pass the related charge to an output that is coupled to a charge store. The input and output of the pass gate are subjected to variations in voltage levels creating transient voltage potential relationships between the input (e.g., source), the output (e.g., drain), and the pass gate substrate (e.g., bulk node). Such fluctuations are accommodated through continuous monitoring of the input and output terminals and, when appropriate, coupling the corresponding potential as exhibited at one of the input or output terminals to the substrate or bulk node of the pass gate.
摘要翻译：偏置电路，适用于电荷泵环境，用于将适当的端子电压电位耦合到体积节点。具体地，诸如集成电路的晶体管的通过栅极操作以隔离来自诸如电荷泵倍压器的升压装置的升压电压输入，并将相关电荷转移或传递到耦合到电荷的输出商店。通过栅极的输入和输出受到电压电平变化，从而产生输入（例如，源极），输出（例如漏极）和通过栅极衬底（例如，体节点）之间的瞬态电压电位关系。这种波动通过对输入和输出端子的连续监测以及适当时将在一个输入或输出端子处显示的相应电位耦合到通孔的基板或体积节点来适应。

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