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1. 发明授权

US08456926B2 Memory write error correction circuit 有权
标题翻译：内存写错误纠正电路
公开(公告)号：US08456926B2
公开(公告)日：2013-06-04
申请号：US13013616
申请日：2011-01-25
申请人： Adrian E. Ong , Vladimir Nitikin
发明人： Adrian E. Ong , Vladimir Nitikin
IPC分类号： G11C7/00 , G11C8/00 , G11C11/00
CPC分类号： G11C7/1006 , G11C7/22 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C2211/5647
摘要： Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.
摘要翻译：存储电路包括阵列，行解码器，列解码器，用于接收数据位的地址的寻址电路，控制逻辑接收命令并向存储器系统块发送控制信号，以及感测和写入耦合到所选列的驱动器电路。隐藏的读取比较电路耦合在感测电路和写入驱动器之间，该驱动器响应于输入锁存器中的数据位与从存储器阵列读取的数据输出之间的比较将错误标志耦合到控制逻辑电路。写错误地址标签存储器响应于错误标志，并且经由双向总线耦合到寻址电路。提供了具有用于发送和接收所述数据位的第一和第二双向总线的数据输入输出电路。写错误地址标签存储器如果设置了错误标志，则存储地址，并在重写操作期间提供地址。

2. 发明申请

US20120127804A1 Memory Write Error Correction Circuit 有权
标题翻译：内存写错误纠正电路
公开(公告)号：US20120127804A1
公开(公告)日：2012-05-24
申请号：US13013616
申请日：2011-01-25
申请人： Adrian E. Ong , Vladimir Nitikin
发明人： Adrian E. Ong , Vladimir Nitikin
IPC分类号： G11C7/00 , G11C8/06
CPC分类号： G11C7/1006 , G11C7/22 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C2211/5647
摘要： Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.
摘要翻译：存储电路包括阵列，行解码器，列解码器，用于接收数据位的地址的寻址电路，控制逻辑接收命令并向存储器系统块发送控制信号，以及感测和写入耦合到所选列的驱动器电路。隐藏的读取比较电路耦合在感测电路和写入驱动器之间，该驱动器响应于输入锁存器中的数据位与从存储器阵列读取的数据输出之间的比较将错误标志耦合到控制逻辑电路。写错误地址标签存储器响应于错误标志，并且经由双向总线耦合到寻址电路。提供了具有用于发送和接收所述数据位的第一和第二双向总线的数据输入输出电路。写错误地址标签存储器如果设置了错误标志，则存储地址，并在重写操作期间提供地址。

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