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1. 发明授权

US10014037B2 Semiconductor memory package including memory device with inverting circuit 有权
公开(公告)号：US10014037B2
公开(公告)日：2018-07-03
申请号：US15490614
申请日：2017-04-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyo-min Sohn
IPC分类号： G11C7/00 , G11C7/10 , G11C5/02 , G11C5/06 , G11C7/22 , G11C7/12
CPC分类号： G11C7/1009 , G11C5/02 , G11C5/06 , G11C7/1006 , G11C7/1045 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/1675 , G11C11/4085 , G11C11/4096 , G11C11/4097 , G11C2211/5647
摘要： A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

2. 发明申请

US20170269839A1 ERROR CORRECTION CODE PROCESSING AND DATA SHAPING 审中-公开
公开(公告)号：US20170269839A1
公开(公告)日：2017-09-21
申请号：US15073373
申请日：2016-03-17
申请人： SANDISK TECHNOLOGIES INC.
发明人： Idan Alrod , Eran Sharon , Ariel Navon
IPC分类号： G06F3/06 , G11C29/52 , G06F11/10
CPC分类号： G06F3/0604 , G06F3/064 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G06F2212/40 , G06F2212/401 , G06F2212/403 , G11C16/34 , G11C16/3418 , G11C16/349 , G11C16/3495 , G11C29/52 , G11C2211/5647
摘要： A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.

3. 发明申请

US20170221534A1 SEMICONDUCTOR MEMORY PACKAGE 审中-公开
公开(公告)号：US20170221534A1
公开(公告)日：2017-08-03
申请号：US15490614
申请日：2017-04-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyo-min SOHN
IPC分类号： G11C7/10 , G11C7/12 , G11C7/22 , G11C5/02 , G11C5/06
CPC分类号： G11C7/1009 , G11C5/02 , G11C5/06 , G11C7/1006 , G11C7/1045 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/1675 , G11C11/4085 , G11C11/4096 , G11C11/4097 , G11C2211/5647
摘要： A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.

4. 发明申请

US20170154658A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20170154658A1
公开(公告)日：2017-06-01
申请号：US15432287
申请日：2017-02-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiromitsu KOMAI
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C7/1051 , G11C7/106 , G11C16/0483 , G11C16/08 , G11C2211/5642 , G11C2211/5647
摘要： According to one embodiment, a semiconductor memory device includes a plurality of data latches; and an inverter shared by the plurality of data latches. The inverter is inserted between complementary buses that sandwich the plurality of data latches.

5. 发明申请

US20160378400A1 MEMORY HEALTH MONITORING 有权
标题翻译：记忆健康监测
公开(公告)号：US20160378400A1
公开(公告)日：2016-12-29
申请号：US14924615
申请日：2015-10-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： NIAN NILES YANG , IDAN ALROD
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0616 , G06F3/0679 , G11C7/1006 , G11C16/3495 , G11C2211/5647
摘要： A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.
摘要翻译：数据存储设备可以被配置为将第一数据写入非易失性存储器的第一组存储元件，并将第二数据写入非易失性存储器的第二组存储元件。可以通过数据整形操作来处理第一数据，并且可以不通过数据整形操作来处理第二数据。数据存储设备还可以被配置为从第二组存储单元读取第二数据的表示，并且基于第二数据的表示来确定非易失性存储器的一部分的块健康度量。该部分可以包括第一组存储元件和第二组存储元件。作为说明性的非限制性示例，第一部分可以是非易失性存储器的第一块。

6. 发明授权

US09047975B2 Coding techniques for reducing write cycles for memory 有权
标题翻译：用于减少存储器写周期的编码技术
公开(公告)号：US09047975B2
公开(公告)日：2015-06-02
申请号：US13687147
申请日：2012-11-28
申请人： ADESTO TECHNOLOGIES CORPORATION
发明人： Ravi Sunkavalli , Malcolm Wing
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C16/34 , G06F12/02 , G11C16/00 , G11C11/56 , G11C7/10 , G11C13/00 , H03M13/23 , G06F11/10
CPC分类号： G11C16/349 , G06F11/1048 , G06F12/0238 , G11C7/1006 , G11C11/5614 , G11C11/5628 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C16/00 , G11C16/3495 , G11C2211/5641 , G11C2211/5646 , G11C2211/5647 , G11C2211/5648 , H03M13/23
摘要： Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device.
摘要翻译：本文公开了用于编码数据以减少半导体存储器件中的写入周期的结构和方法。在一个实施例中，向半导体存储器件写入数据的方法可以包括：（i）确定要写入半导体存储器件的数据的有效位数; （ii）确定与要写入半导体存储器件的数据相关联的标签，其中基于确定的有效位数量来确定标签; （iii）当标签具有第一状态时对数据进行编码，其中标签被配置为指示数据编码，其包括使用编码数据的N位来存储数据的M位，其中M和N都是正整数，N 大于M; 和（iv）在半导体存储器件中写入编码数据和标签。

7. 发明授权

US08862964B2 Data storage in analog memory cells using a non-integer number of bits per cell 有权
标题翻译：使用每个单元的非整数位的模拟存储单元中的数据存储
公开(公告)号：US08862964B2
公开(公告)日：2014-10-14
申请号：US14147714
申请日：2014-01-06
申请人： Apple Inc.
发明人： Avraham Meir , Micha Anholt , Naftali Sommer , Eyal Gurgi
IPC分类号： G11C29/00 , G11C27/00 , G06F11/10 , G11C16/04 , G11C16/12
CPC分类号： G11C27/005 , G06F11/1048 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5647 , G11C2211/5648
摘要： A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels.
摘要翻译：一种用于数据存储的方法包括在第一编程阶段通过将该组中的存储器单元编程为一组初始编程级别来将第一数据存储在一组模拟存储器单元中。在第一编程阶段之后的第二编程阶段，通过以下方式将第二数据存储在组中：将在第一编程阶段中编程的组中的存储器单元识别为初始编程的预定义部分子集中的相应电平水平; 以及仅使用所述第二数据来编程所识别的存储器单元，以便将所识别的存储器单元中的至少一些设置为与所述初始编程级别不同的一个或多个附加编程级别。

8. 发明授权

US08762626B2 Data modification based on matching bit patterns 有权
标题翻译：基于匹配位模式的数据修改
公开(公告)号：US08762626B2
公开(公告)日：2014-06-24
申请号：US13272648
申请日：2011-10-13
申请人： Omprakash Bisen , Abdulla Pichen
发明人： Omprakash Bisen , Abdulla Pichen
IPC分类号： G06F12/00 , G06F12/02 , G06F11/10 , G11C11/56 , G11C29/42 , G11C16/04
CPC分类号： G06F12/0246 , G06F11/1072 , G06F2212/7201 , G11C11/5628 , G11C16/0483 , G11C2211/5647
摘要： A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.
摘要翻译：数据存储装置包括存储器和控制器。控制器被配置为识别与第一组位模式中的任何位模式匹配的位组。比特组中的每一个包括要存储在存储器中的第一数据的第一位，第二数据的第二位和第三数据的第三位。响应于确定所识别的组的计数超过阈值，控制器被配置为改变第一数据的多个比特。改变第一数据的多个位减少与第一组位模式中的任何位模式相匹配的位组组的数量。

9. 发明授权

US08756464B2 Flash memory device and flash memory programming method equalizing wear-level 有权
标题翻译：闪存设备和闪存编程方法均衡磨损等级
公开(公告)号：US08756464B2
公开(公告)日：2014-06-17
申请号：US12811001
申请日：2008-08-25
申请人： Bumsoo Kim , Hyunmo Chung , Hanmook Park
发明人： Bumsoo Kim , Hyunmo Chung , Hanmook Park
IPC分类号： G11C29/00 , H03M13/00 , G11C11/34 , G11C5/14 , G06F13/00 , G11C16/34 , G11C16/10 , G11C11/56 , G11C29/36 , G11C13/00 , G06F3/06 , G06F11/00 , G06F11/07 , G06F11/08 , G06F12/02 , G06F17/30
CPC分类号： G11C16/3495 , G06F3/0679 , G06F11/00 , G06F11/0727 , G06F11/08 , G06F12/0246 , G06F17/30218 , G11C11/5628 , G11C13/0035 , G11C16/10 , G11C16/26 , G11C16/3436 , G11C16/344 , G11C16/349 , G11C29/36 , G11C2211/5647
摘要： Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.
摘要翻译：公开了一种使磨损等级化的闪速存储器件和闪存编程方法。闪速存储器件包括存储单元阵列，反转确定单元，用于通过基于数据页中的“1”和“0”的数量来反转或不反相数据页生成编程页面，编程单元，用于存储所生成的编程页面在存储单元阵列中; 以及数据验证单元，用于读取存储在存储单元阵列中的编程页面，以根据读取编程页面中是否存在错误从编程页面恢复数据页面，并输出恢复的数据页面，从而可以均衡存储单元的磨损级别。

10. 发明授权

US08724382B2 Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same 有权
标题翻译：具有极性控制的多单元（MBC）非易失性存储装置和系统的编程方法相同
公开(公告)号：US08724382B2
公开(公告)日：2014-05-13
申请号：US13117715
申请日：2011-05-27
申请人： Jin-Ki Kim , William Francis Petrie
发明人： Jin-Ki Kim , William Francis Petrie
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C29/00 , G11C2211/5646 , G11C2211/5647
摘要： A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.
摘要翻译：一种多比特单元（MBC）非易失性存储装置，方法和系统，其中用于向/从存储器阵列写入/读取数据的控制器通过选择性地反转数据字来控制数据的极性，以最大化位数（M-1）个虚拟页面内编程，并选择性地反转数据字以最小化要在第M个虚拟页面中编程的位数，其中M是每个单元的位数。当数据字反转时，设置相应的极性控制标志。当从M个虚拟页面读取时，根据相应的极性标志选择性地反转数据。许多最高阈值电压编程状态在减少。这提供了编程单元阈值电压的更严格的分配，降低的功耗，减少的编程时间和增强的器件可靠性。

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