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    • 4. 发明授权
    • Method, device and system for activating on-line patch
    • 用于激活在线补丁的方法,设备和系统
    • US09075692B2
    • 2015-07-07
    • US13336227
    • 2011-12-23
    • Jiaqiang YuWei Zheng
    • Jiaqiang YuWei Zheng
    • G06F9/445
    • G06F8/67G06F8/656
    • Embodiments of the present invention provide a method, a device and a system for activating an on-line patch. The method comprises: positioning an address of a patch function and an entry address of a to-be-patched function; writing, in a middle segment, a long-jump instruction for jumping to the patch function based on the address of the patch function and the entry address of the to-be-patched function, where the middle segment is a storage space, which is located before or after the entry position of the to-be-patched function and can at least store one long-jump instruction; and modifying an instruction at the entry position of the to-be-patched function to a short-jump instruction for jumping to the middle segment, so as to jump to the middle segment after the short jump instruction is executed, and then to jump to and execute the patch function through that instructions in the middle segment are executed.
    • 本发明的实施例提供一种用于激活在线补丁的方法,装置和系统。 该方法包括:定位补丁功能的地址和待修补功能的入口地址; 在中间段中,根据补丁功能的地址和待修补功能的入口地址写入跳转到补丁功能的长跳转指令,其中中间段是存储空间,其中 位于待修补功能的入口位置之前或之后,并且可以至少存储一个长跳转指令; 并且将待修补功能的入口位置处的指令修改为跳转到中间段的短跳转指令,以便在执行短跳转指令之后跳转到中间段,然后跳转到 并通过中间段的指令执行补丁功能。
    • 8. 发明授权
    • Memory devices containing a high-K dielectric layer
    • 包含高K电介质层的存储器件
    • US08691647B1
    • 2014-04-08
    • US10927692
    • 2004-08-27
    • Wei ZhengArvind HalliyalMark T. RamsbeyJack F. Thomas
    • Wei ZhengArvind HalliyalMark T. RamsbeyJack F. Thomas
    • H01L21/336
    • H01L21/28273H01L21/28282H01L29/513H01L29/517H01L29/7881
    • In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO2.
    • 在一个实施例中,公开了一种半导体器件。 所述半导体器件形成在具有有源区的半导体衬底上,所述半导体器件包括:栅极电介质层,其设置在所述半导体衬底上,所述栅极电介质层具有至少两个具有至少一个具有电介质的子层的子层 常数大于SiO2; 形成在所述栅介质层上的浮置栅极,限定插入在所述半导体衬底的有源区域内形成的源极和漏极之间的沟道; 形成在浮动栅极上方的控制栅极; 以及插入在所述浮置栅极和所述控制栅极之间的隔间介电层,所述栅极间介电层包括:形成在所述浮动栅极上的第一层; 形成在所述第一层上的第二层; 以及形成在第二层上的第三层,其中第一层,第二层和第三层中的每一层具有大于SiO 2的介电常数。