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    • 2. 发明授权
    • Cache data migration in a multicore processing system
    • 在多核处理系统中缓存数据迁移
    • US09135172B2
    • 2015-09-15
    • US13565140
    • 2012-08-02
    • Jian LiangJian Shen
    • Jian LiangJian Shen
    • G06F12/00G06F12/08
    • G06F12/0806G06F12/0893Y02D10/13
    • A method of transferring data between two caches comprises sending a first message from a first processor to a second processor indicating that data is available for transfer from a first cache associated with the first processor, requesting, from the second processor, a data transfer of the data from the first cache to a second cache associated with the second processor, transferring the data from the first cache to the second cache in response to the request, and sending a second message from the second processor to the first processor indicating that the data transfer is complete.
    • 一种在两个高速缓存之间传送数据的方法包括从第一处理器向第二处理器发送指示数据可用于从与第一处理器相关联的第一高速缓存传送的第一消息,从第二处理器请求来自第二处理器的数据传送 从第一高速缓存到与第二处理器相关联的第二缓存器的数据,响应于该请求将数据从第一高速缓存传送到第二高速缓存,以及从第二处理器向第一处理器发送指示数据传送的第二消息 做完了。
    • 5. 发明授权
    • Register file system and method for pipelined processing
    • 注册文件系统和流水线处理方法
    • US08725991B2
    • 2014-05-13
    • US11853866
    • 2007-09-12
    • Lin WangMasud KamalPaul BassettSuresh VenkumahantiJian Shen
    • Lin WangMasud KamalPaul BassettSuresh VenkumahantiJian Shen
    • G06F9/30G06F9/40G06F15/00
    • G06F9/3851G06F9/30123G06F9/30141G06F13/4252Y02D10/14Y02D10/151
    • The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file.
    • 本公开包括多线程处理器,其包括与第一线程相关联的第一寄存器文件和与第二线程相关联的第二寄存器文件。 至少一个硬件资源由第一和第二寄存器文件共享。 此外,第一线程可以具有与第二线程不连续的管线访问位置。 还公开了一种访问多个寄存器文件的方法。 该方法包括从第一寄存器文件读取数据,同时从第二寄存器堆读取数据。 第一寄存器文件与第一指令流相关联,并且第二寄存器文件与第二指令流相关联。 第一指令流在处理器的执行流水线中与第二指令流相顺序,并且第一寄存器文件相对于第二寄存器文件位于非相邻位置。
    • 7. 发明授权
    • Voltage level shifter
    • 电压电平转换器
    • US08614700B2
    • 2013-12-24
    • US13099462
    • 2011-05-03
    • Jian-Shen Yu
    • Jian-Shen Yu
    • G09G5/00
    • G09G3/3685G09G2310/0289
    • A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.
    • 由单型晶体管形成的电压电平移位器包括两个输入端子,两个电源端子,多个薄膜晶体管和输出端子。 由单一型晶体管形成的另一个电压电平移位器包括两个输入端子,一个输出端子,两个电源端子,两个输入单元,第一薄膜晶体管,禁用单元,反馈单元和第二薄膜晶体管 。 电压电平移位器由单型TFT形成。 当将电压电平移位器集成到TFT显示器的基板中时,简化了制造工艺。 此外,节电。