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1. 发明授权

US08593197B1 Delay line circuit, delay locked loop and tester system including the same 有权
标题翻译：延迟线路电路，延迟锁定环路和测试仪系统包括相同
公开(公告)号：US08593197B1
公开(公告)日：2013-11-26
申请号：US13606019
申请日：2012-09-07
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03H11/26
CPC分类号： H03L7/0812
摘要： The invention provides a delay line circuit. The delay line circuit includes a delay line section and a feedback selection section. The delay line section receives an input clock signal and a feedback clock signal and delays one of the input clock signal and the feedback clock signal to generate an output clock signal, wherein the delay line section includes a plurality of delay units coupled in series. The feedback selection section is coupled to the delay line section and feedbacks the output clock signal to one of the delay units to serve as the feedback clock signal based on a selection signal. Wherein, one of the input clock signal and the feedback clock signal is delayed by a specific number of the delay units based on the selection signal to changes the frequency of the output clock signal.
摘要翻译：本发明提供一种延迟线电路。延迟线电路包括延迟线部分和反馈选择部分。延迟线部分接收输入时钟信号和反馈时钟信号，并延迟输入时钟信号和反馈时钟信号之一以产生输出时钟信号，其中延迟线部分包括串联耦合的多个延迟单元。反馈选择部分耦合到延迟线部分，并且基于选择信号将输出时钟信号反馈到延迟单元之一以用作反馈时钟信号。其中，基于选择信号将输入时钟信号和反馈时钟信号之一延迟特定数量的延迟单元，以改变输出时钟信号的频率。

2. 发明申请

US20110080793A1 SENSING AMPLIFIER APPLIED TO AT LEAST A MEMORY CELL, MEMORY DEVICE, AND ENHANCEMENT METHOD FOR BOOSTING THE SENSING AMPLIFIER THEREOF 有权
标题翻译：感应放大器适用于至少一个存储器单元，存储器件以及用于增强其感测放大器的增强方法
公开(公告)号：US20110080793A1
公开(公告)日：2011-04-07
申请号：US12573155
申请日：2009-10-05
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/4094
摘要： A sensing amplifier consists of a sensing circuit, a boosting circuit, at least one bit-line isolating circuit, and at least a P-sensing enhancement circuit. The sensing circuit is disposed between a sensing line and a complementary sensing line. The boosting circuit boosts the sensing line and the complementary sensing line during a boosting stage. The bit-line isolating circuit is coupled to the sensing circuit for controlling whether to isolate a bit line/complementary bit line from the sensing line/complementary sensing line. The P-sensing enhancement circuit is coupled to the sensing line, the complementary sensing line, and a reference voltage. When the bit-line isolating circuit isolates the bit line from the sensing line and isolates the complementary bit line from the complementary sensing line, a voltage level of the bit line or the complementary bit line is pulled up to the reference voltage by the P-sensing enhancement circuit during an enhancement stage.
摘要翻译：感测放大器由感测电路，升压电路，至少一个位线隔离电路和至少P感测增强电路组成。感测电路设置在感测线和互补感测线之间。升压电路在升压阶段增强感测线和互补感测线。位线隔离电路耦合到感测电路，用于控制是否将位线/互补位线与感测线/互补感测线隔离开来。 P感测增强电路耦合到感测线，互补感测线和参考电压。当位线隔离电路将位线与感测线隔离并且将互补位线与互补感测线隔离时，位线或互补位线的电压电平被P- 增强阶段的感测增强电路。

3. 发明授权

US07724055B2 Clock receivers 有权
标题翻译：时钟接收机
公开(公告)号：US07724055B2
公开(公告)日：2010-05-25
申请号：US11970987
申请日：2008-01-08
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03K3/017
CPC分类号： G06F1/10 , H04L25/0272 , H04L27/0014 , H04L2027/0036 , H04L2027/0046 , H04L2027/0067
摘要： A clock receiver is provided. A receiving unit receives a pair of complementary clocks and generates a first clock, and a calibration unit detects whether a cross point of the complementary clocks has shifted, generates a detected result and accordingly adjusts toggling of the first clock.
摘要翻译：提供时钟接收器。接收单元接收一对互补时钟并产生第一时钟，并且校准单元检测互补时钟的交叉点是否已经移位，产生检测结果，并因此调整第一时钟的切换。

4. 发明申请

US20080290920A1 DUTY CYCLE CORRECTION CIRCUIT AND METHOD THEREOF 有权
标题翻译：占空比校正电路及其方法
公开(公告)号：US20080290920A1
公开(公告)日：2008-11-27
申请号：US11925338
申请日：2007-10-26
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.
摘要翻译：占空比校正电路包括分频器，占空比检测器和延迟电路。分频器接收第一时钟信号并且分频第一时钟信号的频率以产生第二时钟信号。占空比检测器接收第二时钟信号和校正时钟信号，并根据第二时钟信号和校正时钟信号产生控制信号。延迟电路接收第一时钟信号和控制信号，并根据控制信号调整第一时钟信号的下降沿的延迟时间，以产生校正时钟。

5. 发明授权

US07450443B2 Phase detection method, memory control method, and related device 有权
标题翻译：相位检测方法，存储器控制方法及相关设备
公开(公告)号：US07450443B2
公开(公告)日：2008-11-11
申请号：US11617737
申请日：2006-12-29
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C7/00 , G11C8/00 , G11C8/18 , G01R29/00
CPC分类号： G11C7/22 , G11C7/222
摘要： A phase detection method for detecting a phase difference between a data strobe signal and a clock signal, includes: latching the clock signal according to the data strobe signal to generate a phase lead/lag detection result; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal according to the delayed data strobe signals to generate a plurality of phase detection results corresponding to the delayed data strobe signals, respectively; and if the phase lead/lag detection result indicates that the data strobe signal leads the clock signal, utilizing the phase detection results to represent the phase difference between the data strobe signal and the clock signal. A memory control method and a memory control circuit respectively corresponding to the phase detection method are further provided.
摘要翻译：用于检测数据选通信号和时钟信号之间的相位差的相位检测方法包括：根据数据选通信号锁存时钟信号以产生相位超前/滞后检测结果; 延迟数据选通信号以产生多个延迟的数据选通信号; 根据延迟的数据选通信号锁存时钟信号，分别产生与延迟的数据选通信号对应的多个相位检测结果; 并且如果相位超前/滞后检测结果指示数据选通信号引导时钟信号，则利用相位检测结果来表示数据选通信号和时钟信号之间的相位差。还提供分别对应于相位检测方法的存储器控制方法和存储器控制电路。

6. 发明授权

US07417905B2 Apparatus and related method for controlling switch module in memory by detecting operating frequency of specific signal in memory 有权
标题翻译：通过检测存储器中特定信号的操作频率来控制存储器中的开关模块的装置和相关方法
公开(公告)号：US07417905B2
公开(公告)日：2008-08-26
申请号：US11563213
申请日：2006-11-27
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C8/18
摘要： An apparatus for controlling a switch module in a memory is disclosed. A first pulse width adjusting unit receives an input instruction signal and adjusts a pulse width of the input instruction signal to generate an adjusted input instruction signal according to a first pulse width adjustment. A decoder receives an input address signal and the adjusted input instruction signal to generate a control signal utilized for controlling a turn-on period of the switch module. A second pulse width adjusting unit receives the control signal and adjusts a pulse width of the control signal to generate an adjusted control signal according to a second pulse width adjustment. A frequency detector controls the first and second pulse width adjusting units to set the first and second pulse width adjustments according to a frequency of a specific signal in the memory.
摘要翻译：公开了一种用于控制存储器中的开关模块的装置。第一脉冲宽度调整单元接收输入指令信号并根据第一脉冲宽度调整调节输入指令信号的脉冲宽度以产生经调整的输入指令信号。解码器接收输入地址信号和经调整的输入指令信号，以产生用于控制开关模块的导通周期的控制信号。第二脉冲宽度调整单元接收控制信号并调节控制信号的脉冲宽度，以根据第二脉冲宽度调整产生经调节的控制信号。频率检测器控制第一和第二脉冲宽度调节单元，以根据存储器中特定信号的频率设置第一和第二脉冲宽度调节。

7. 发明申请

US20080122492A1 FREQUENCY DETECTOR UTILIZING A PULSE GENERATOR, AND MEHTOD THEREOF 有权
标题翻译：利用脉冲发生器的频率检测器及其测量
公开(公告)号：US20080122492A1
公开(公告)日：2008-05-29
申请号：US11562415
申请日：2006-11-22
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G01R23/02 , H03K5/153
CPC分类号： H03K5/159
摘要： The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.
摘要翻译：本发明公开了一种用于检测输入时钟的频率的频率检测装置。频率检测装置包括：脉冲发生器，数字信号发生器和解码器。脉冲发生器耦合到输入时钟，用于提取输入时钟的周期以产生脉冲，并且数字信号发生器耦合到脉冲发生器，用于将脉冲转换成多个逻辑值。数字信号发生器包括：延迟模块，其耦合到所述脉冲，用于延迟所述脉冲以分别根据多个延迟量产生多个延迟的脉冲; 以及耦合到延迟模块的采样模块，用于对脉冲进行采样，以分别根据延迟的脉冲产生逻辑值。解码器耦合到数字信号发生器，用于根据逻辑值确定输入时钟的频率。

8. 发明申请

US20080062780A1 PHASE DETECTION METHOD, MEMORY CONTROL METHOD, AND RELATED DEVICE 有权
标题翻译：相位检测方法，存储器控制方法和相关装置
公开(公告)号：US20080062780A1
公开(公告)日：2008-03-13
申请号：US11617737
申请日：2006-12-29
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222
摘要： A phase detection method for detecting a phase difference between a data strobe signal and a clock signal, includes: latching the clock signal according to the data strobe signal to generate a phase lead/lag detection result; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal according to the delayed data strobe signals to generate a plurality of phase detection results corresponding to the delayed data strobe signals, respectively; and if the phase lead/lag detection result indicates that the data strobe signal leads the clock signal, utilizing the phase detection results to represent the phase difference between the data strobe signal and the clock signal. A memory control method and a memory control circuit respectively corresponding to the phase detection method are further provided.
摘要翻译：用于检测数据选通信号和时钟信号之间的相位差的相位检测方法包括：根据数据选通信号锁存时钟信号以产生相位超前/滞后检测结果; 延迟数据选通信号以产生多个延迟的数据选通信号; 根据延迟的数据选通信号锁存时钟信号，分别产生与延迟的数据选通信号对应的多个相位检测结果; 并且如果相位超前/滞后检测结果指示数据选通信号引导时钟信号，则利用相位检测结果来表示数据选通信号和时钟信号之间的相位差。还提供分别对应于相位检测方法的存储器控制方法和存储器控制电路。

9. 发明授权

US07280419B1 Latency counter having frequency detector and latency counting method thereof 有权
标题翻译：具有频率检测器和延迟计数方法的延迟计数器
公开(公告)号：US07280419B1
公开(公告)日：2007-10-09
申请号：US11556195
申请日：2006-11-03
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222
摘要： The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one delay amount to the input clock to generate a delayed input clock; a frequency detector for detecting a frequency of a specific signal of the memory to set the delay amount; and a delay control signal generating module for generating a first delayed control signal and a second delayed control signal corresponding to the delayed input clock and the memory accessing control signal respectively, wherein timing of the first delayed control signal is earlier than timing of the second delayed control signal.
摘要翻译：本发明公开了一种应用于存储器的等待时间计数器，用于延迟存储器访问控制信号。延迟计数器包括：时钟延迟模块，用于向输入时钟施加至少一个延迟量以产生延迟的输入时钟; 频率检测器，用于检测存储器的特定信号的频率以设置延迟量; 以及延迟控制信号产生模块，用于分别产生与延迟的输入时钟和存储器访问控制信号相对应的第一延迟控制信号和第二延迟控制信号，其中第一延迟控制信号的定时早于第二延迟控制信号的定时控制信号。

10. 发明申请

US20140049302A1 PHASE-LOCKED LOOP AND METHOD FOR CLOCK DELAY ADJUSTMENT 有权
标题翻译：相位锁定环和时钟延迟调整方法
公开(公告)号：US20140049302A1
公开(公告)日：2014-02-20
申请号：US13590185
申请日：2012-08-20
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03L7/06
CPC分类号： H03L7/0995
摘要： A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal.In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.
摘要翻译：公开了一种用于时钟延迟调整的锁相环（PLL）及其方法。该方法包括以下步骤。产生参考时钟信号和时钟信号。参考时钟信号通过N分频器馈送以产生具有参考时钟信号的频率1 / N的输出时钟信号。在相位频率检测器中，根据相位差和输出时钟信号与耦合到相位频率检测器的压控振荡器产生的反馈信号之间的频率差产生控制信号。然后通过电荷泵和环路滤波器馈送控制信号，以根据控制信号产生电压控制信号。此外，在可调延迟元件中，根据时钟信号和电压控制信号产生混合延迟信号。

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