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1. 发明授权

US09354274B2 Circuit test system electric element memory control chip under different test modes 有权
标题翻译：电路测试系统电气元件存储控制芯片在不同的测试模式下
公开(公告)号：US09354274B2
公开(公告)日：2016-05-31
申请号：US13584792
申请日：2012-08-13
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G01R31/28 , G01R31/317 , G11C29/12 , G11C29/14
CPC分类号： G01R31/31712 , G01R31/31716 , G01R31/31717 , G01R31/31725 , G01R31/31727 , G11C29/12015 , G11C29/14
摘要： A circuit test system including a circuit test apparatus and a circuit to be tested is provided. The circuit test apparatus provides a first clock signal. The circuit to be tested includes a plurality of input/output pads and at least one clock pad. At least two input/output pads of the input/output pads are connected to each other to form a test loop during a test mode. The clock pad receives the first clock signal. The circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the test loop of the circuit to be tested is tested based on the second clock signal during the test mode. The frequency of the second clock signal is higher than that of the first clock signal. Furthermore, a circuit test method of the foregoing circuit test system is also provided.
摘要翻译：提供一种包括电路测试装置和待测试电路的电路测试系统。电路测试装置提供第一时钟信号。要测试的电路包括多个输入/输出焊盘和至少一个时钟焊盘。在测试模式期间，输入/输出焊盘的至少两个输入/输出焊盘彼此连接以形成测试回路。时钟垫接收第一个时钟信号。要测试的电路将第一时钟信号的频率乘以产生第二时钟信号，并且在测试模式期间基于第二时钟信号来测试待测电路的测试回路。第二时钟信号的频率高于第一时钟信号的频率。此外，还提供了上述电路测试系统的电路测试方法。

2. 发明授权

US08791737B2 Phase-locked loop and method for clock delay adjustment 有权
标题翻译：锁相环和时钟延迟调整方法
公开(公告)号：US08791737B2
公开(公告)日：2014-07-29
申请号：US13590185
申请日：2012-08-20
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03L7/06
CPC分类号： H03L7/0995
摘要： A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.
摘要翻译：公开了一种用于时钟延迟调整的锁相环（PLL）及其方法。该方法包括以下步骤。产生参考时钟信号和时钟信号。参考时钟信号通过N分频器馈送以产生具有参考时钟信号的频率1 / N的输出时钟信号。在相位频率检测器中，根据相位差和输出时钟信号与耦合到相位频率检测器的压控振荡器产生的反馈信号之间的频率差产生控制信号。然后通过电荷泵和环路滤波器馈送控制信号，以根据控制信号产生电压控制信号。此外，在可调延迟元件中，根据时钟信号和电压控制信号产生混合延迟信号。

3. 发明授权

US07786764B2 Signal receiver and voltage compensation method thereof 有权
标题翻译：信号接收机及其电压补偿方法
公开(公告)号：US07786764B2
公开(公告)日：2010-08-31
申请号：US12406943
申请日：2009-03-18
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03K5/153
CPC分类号： H03F3/45183 , H03F3/45766 , H03F2203/45628
摘要： A signal receiver includes a first-stage circuit, a second-stage circuit, a current compensation circuit, and a biasing circuit. A first input end of the first-stage circuit receives a reference voltage, and a second end of the first-stage circuit receives an input signal. A first input end and a second input end of the second-stage circuit are respectively coupled to a first output end and a second output end of the first-stage circuit. The current compensation circuit is coupled to the first input end of the second-stage circuit for dynamically providing a compensation current to the first input end of the second-stage circuit in response to a biasing voltage, so as to stabilize its voltage level. The biasing circuit biases the first-stage circuit and the current compensation circuit and sets the biasing voltage of the current compensation circuit in response to the reference voltage.
摘要翻译：信号接收机包括第一级电路，第二级电路，电流补偿电路和偏置电路。第一级电路的第一输入端接收参考电压，第一级电路的第二端接收输入信号。第二级电路的第一输入端和第二输入端分别耦合到第一级电路的第一输出端和第二输出端。电流补偿电路耦合到第二级电路的第一输入端，用于响应于偏置电压动态地向第二级电路的第一输入端提供补偿电流，以便稳定其电压电平。偏置电路偏置第一级电路和电流补偿电路，并根据参考电压设置电流补偿电路的偏置电压。

4. 发明申请

US20100188127A1 SIGNAL ADJUSTING SYSTEM AND SIGNAL ADJUSTING METHOD 有权
标题翻译：信号调节系统和信号调整方法
公开(公告)号：US20100188127A1
公开(公告)日：2010-07-29
申请号：US12407760
申请日：2009-03-19
申请人： Wen-Chang Cheng , Chuan-Jen Chang
发明人： Wen-Chang Cheng , Chuan-Jen Chang
IPC分类号： H03H11/16
CPC分类号： H03L7/0812
摘要： A signal adjusting system includes: a signal generating device for generating a plurality of output signals according to a plurality of pre-output signals, a plurality of signal transmitting paths being coupled to the signal generating device for transmitting the plurality of output signals; and a controlling device coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to a first output signal and a second transmitted signal corresponding to a second output signal, and detecting a phase different between the first transmitted signal and the second transmitted signal to generate a detected result to the signal generating device, wherein the signal generating device adjusts the phase difference between the first output signal and the second output signal according to the detected result.
摘要翻译：信号调整系统包括：信号发生装置，用于根据多个预输出信号产生多个输出信号;多个信号发送路径，耦合到信号发生装置，用于发送多个输出信号; 以及控制装置，其耦合到所述多个信号发送路径，用于接收对应于第一输出信号的第一发送信号和对应于第二输出信号的第二发送信号，以及检测所述第一发送信号和所述第二发送信号信号以产生检测结果给信号发生装置，其中信号发生装置根据检测结果调整第一输出信号和第二输出信号之间的相位差。

5. 发明授权

US07675335B1 Phase detecting module and related phase detecting method 有权
标题翻译：相位检测模块及相位相位检测方法
公开(公告)号：US07675335B1
公开(公告)日：2010-03-09
申请号：US12407787
申请日：2009-03-19
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/0891
摘要： A phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is arranged to compare a first input signal and a second input signal to generate a phase detecting result. The comparator is arranged to compare the phase detecting result and a predetermined voltage to generate a comparing result. The counter is arranged to count one of the first input signal and the second input signal to generate a counting value. The phase detecting result and the counting value are reset if the counting value reaches a predetermined value, and the comparing result is outputted to a target device from the comparator if the counting value reaches a predetermined value.
摘要翻译：相位检测模块包括相位检测单元，比较器和计数器。相位检测单元被配置为比较第一输入信号和第二输入信号以产生相位检测结果。比较器被配置为比较相位检测结果和预定电压以产生比较结果。计数器被配置为对第一输入信号和第二输入信号之一进行计数以产生计数值。如果计数值达到预定值，则相位检测结果和计数值被复位，如果计数值达到预定值，则比较结果从比较器输出到目标装置。

6. 发明授权

US07427879B2 Frequency detector utilizing pulse generator, and method thereof 有权
标题翻译：利用脉冲发生器的频率检测器及其方法
公开(公告)号：US07427879B2
公开(公告)日：2008-09-23
申请号：US11562415
申请日：2006-11-22
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03K9/06
CPC分类号： H03K5/159
摘要： The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values. The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.
摘要翻译：本发明公开了一种用于检测输入时钟的频率的频率检测装置。频率检测装置包括：脉冲发生器，数字信号发生器和解码器。脉冲发生器耦合到输入时钟，用于提取输入时钟的周期以产生脉冲，并且数字信号发生器耦合到脉冲发生器，用于将脉冲转换成多个逻辑值。数字信号发生器包括：延迟模块，耦合到脉冲，用于延迟脉冲以分别根据多个延迟量产生多个延迟的脉冲; 以及耦合到延迟模块的采样模块，用于对脉冲进行采样，以分别根据延迟的脉冲产生逻辑值。解码器耦合到数字信号发生器，用于根据逻辑值确定输入时钟的频率。

7. 发明申请

US20140122948A1 MEMORY TEST SYSTEM AND MEMORY TEST METHOD 有权
标题翻译：内存测试系统和内存测试方法
公开(公告)号：US20140122948A1
公开(公告)日：2014-05-01
申请号：US13666934
申请日：2012-11-01
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C29/04 , G06F11/16
CPC分类号： G11C29/56012 , G11C2029/5602
摘要： A memory test system and a memory test method are provided. The memory test system includes a control unit, a data reading channel, a data writing channel and a test channel. The control unit generates and outputs a first read and a first write command. The data reading channel and the data writing channel coupled to the memory unit, and the control unit respectively reads data from the memory unit at a first time and writes the data back to the memory unit at a second time according to the first read command and the first write command. The test channel receives the data from the data reading channel through an input end and outputs the data back to the data writing channel through an output end after a time delay. The time delay is substantially equal to a time interval between the first time and the second time.
摘要翻译：提供了记忆测试系统和记忆测试方法。存储器测试系统包括控制单元，数据读取通道，数据写入通道和测试通道。控制单元产生并输出第一读取和第一写入命令。所述数据读取通道和所述数据写入通道耦合到所述存储器单元，并且所述控制单元在第一时间分别从所述存储器单元读取数据，并且根据所述第一读取命令在第二时间将所述数据写回所述存储器单元;以及第一个写命令。测试通道通过输入端从数据读取通道接收数据，并在时间延迟后通过输出端将数据输出回数据写入通道。时间延迟基本上等于第一时间和第二时间之间的时间间隔。

8. 发明申请

US20100309737A1 SIGNAL ADJUSTING SYSTEM AND SIGNAL ADJUSTING METHOD 有权
标题翻译：信号调节系统和信号调整方法
公开(公告)号：US20100309737A1
公开(公告)日：2010-12-09
申请号：US12568689
申请日：2009-09-29
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C7/00 , H04L7/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A signal adjusting system includes: a signal generating apparatus for transmitting a first driving signal and a second driving signal, a plurality of signal transmitting paths coupled to the signal generating apparatus, and a controlling apparatus coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to the first driving signal and a second transmitted signal corresponding to the second driving signal, and detecting a phase difference between the first transmitted signal and the second transmitted signal to generate a detected result for the signal generating apparatus, wherein the signal generating apparatus adjusts a first driving ability of the first driving signal and a second driving ability of the second driving signal according to the detected result.
摘要翻译：信号调整系统包括：信号发生装置，用于发送第一驱动信号和第二驱动信号;耦合到信号发生装置的多个信号发送路径;以及耦合到多个信号发送路径的控制装置，用于接收对应于第一驱动信号的第一发送信号和对应于第二驱动信号的第二发送信号，并且检测第一发送信号和第二发送信号之间的相位差，以产生信号发生装置的检测结果，其中信号发生装置根据检测结果来调整第一驱动信号的第一驱动能力和第二驱动信号的第二驱动能力。

9. 发明授权

US07598786B2 Duty cycle correction circuit and method thereof 有权
标题翻译：占空比校正电路及其方法
公开(公告)号：US07598786B2
公开(公告)日：2009-10-06
申请号：US11925338
申请日：2007-10-26
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.
摘要翻译：占空比校正电路包括分频器，占空比检测器和延迟电路。分频器接收第一时钟信号并且分频第一时钟信号的频率以产生第二时钟信号。占空比检测器接收第二时钟信号和校正时钟信号，并根据第二时钟信号和校正时钟信号产生控制信号。延迟电路接收第一时钟信号和控制信号，并根据控制信号调整第一时钟信号的下降沿的延迟时间，以产生校正时钟。

10. 发明授权

US07548470B2 Memory control method and memory control circuit 有权
标题翻译：存储器控制方法和存储器控制电路
公开(公告)号：US07548470B2
公开(公告)日：2009-06-16
申请号：US12242937
申请日：2008-10-01
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： G11C7/00 , G11C8/00 , G11C8/18 , G01R29/00
CPC分类号： G11C7/22 , G11C7/222
摘要： A memory control method includes: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate a plurality of phase detection results in response to the delayed data strobe signals so as to correspond to the delayed data strobe signals; latching write data carried by a data signal according to rising/falling edges of the data strobe signal; performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and in a situation where the data strobe signal leads the clock signal, delaying or bypassing the odd/even data carried by the data separation signal according to the phase detection results. A memory control circuit is provided.
摘要翻译：存储器控制方法包括：响应于数据选通信号，锁存时钟信号以选择性地产生相位超前检测结果和相位滞后检测结果; 延迟数据选通信号以产生多个延迟的数据选通信号; 锁存时钟信号以响应于延迟的数据选通信号而产生多个相位检测结果，以对应于延迟的数据选通信号; 根据数据选通信号的上升/下降沿来锁存数据信号所携带的写入数据; 对写入数据进行奇/偶数据分离，生成携带对应于写入数据的奇/偶数据的数据分离信号; 并且在数据选通信号引导时钟信号的情况下，根据相位检测结果延迟或旁路由数据分离信号携带的奇数/偶数数据。提供存储器控制电路。

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