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1. 发明授权

US08286115B2 Fast routing of custom macros 有权
标题翻译：快速路由自定义宏
公开(公告)号：US08286115B2
公开(公告)日：2012-10-09
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

2. 发明申请

US20100146471A1 FAST ROUTING OF CUSTOM MACROS 有权
标题翻译：快速路由自定义宏
公开(公告)号：US20100146471A1
公开(公告)日：2010-06-10
申请号：US12330664
申请日：2008-12-09
申请人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
发明人： Holger Wetter , Maarten Boersma , Wilhelm Haller , Armin Windschiegl
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/66
摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.
摘要翻译：一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面未布置的布局，并从中创建一个平放布局。

3. 发明申请

US20090112963A1 METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD 审中-公开
标题翻译：在二进制算术加法算术单元中执行两个运算符的执行的方法来执行这种方法
公开(公告)号：US20090112963A1
公开(公告)日：2009-04-30
申请号：US11926582
申请日：2007-10-29
申请人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
发明人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
IPC分类号： G06F7/508
CPC分类号： G06F7/507
摘要： A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
摘要翻译：提供电路所在的方法，电路装置和设计结构，以通过将两个操作数细分为相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算生成对分别包含相同比特位置的两个操作数的特定的比特组的中间结果。每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。

4. 发明授权

US07095252B2 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效
标题翻译：通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享
公开(公告)号：US07095252B2
公开(公告)日：2006-08-22
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/00 , H03K19/20 , H03K19/094
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译：本发明涉及计算机处理器的动态硬件逻辑。特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中每个布置连接在较高电位的所述预充电节点和较低电位之间。

5. 发明申请

US20050040861A1 Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates 失效
标题翻译：通过在复杂的动态多米诺式CMOS门中应用固有的并行性来减少电荷共享
公开(公告)号：US20050040861A1
公开(公告)日：2005-02-24
申请号：US10896836
申请日：2004-07-22
申请人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
发明人： Michael Haase , Wilhelm Haller , Rolf Sautter , Christoph Wandel
IPC分类号： H03K19/096 , H03K19/20
CPC分类号： H03K19/0963
摘要： The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements (24, 26, 28) implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
摘要翻译：本发明涉及计算机处理器的动态硬件逻辑。特别地，本发明涉及一种用于操作实现具有减少的电荷共享的预定逻辑功能的动态逻辑电路的方法和相应的系统。为了进一步减少电荷共享，建议提供预定数量的预先设计的切换布置（24,26,28），其实现与输入变量（A，B，C）的不同组合分布相同的逻辑功能，其中每个布置连接在较高电位的所述预充电节点和较低电位之间。

6. 发明授权

US5634047A Method for executing branch instructions by processing loop end conditions in a second processor 失效
标题翻译：用于通过处理第二处理器中的循环结束条件来执行分支指令的方法
公开(公告)号：US5634047A
公开(公告)日：1997-05-27
申请号：US699074
申请日：1996-06-10
申请人： Klaus J. Getzlaff , Udo Wille , Brigitte Roethe , Wilhelm Haller , Hans-Werner Tast
发明人： Klaus J. Getzlaff , Udo Wille , Brigitte Roethe , Wilhelm Haller , Hans-Werner Tast
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3804 , G06F9/30058 , G06F9/325
摘要： A method and system for executing branch or other instructions in a loop. A loop end condition is evaluated in a fixed point unit while floating point instructions are evaluated in a floating point unit. In a first execution of the instructions in the loop, the loop end condition is processed as in prior art. A branch target instruction is stored in a branch target register and an instruction address of the branch target instruction is stored in a branch address register. However, on subsequent execution of the instructions in the loop, the branch condition is evaluated and, if it is fulfilled, once the end of the loop is detected by comparison of the effective address of the next instruction to be executed with the contents of the branch address register, the effective address of the first instruction in the loop is passed from the branch target register to an operations register.
摘要翻译：用于在循环中执行分支或其他指令的方法和系统。循环结束条件在固定点单元中进行评估，而浮点指令在浮点单元中进行求值。在循环中的指令的第一次执行中，循环结束条件如现有技术那样被处理。分支目标指令存储在分支目标寄存器中，分支目标指令的指令地址存储在分支地址寄存器中。然而，在循环中的指令的随后执行中，评估分支条件，并且如果满足，一旦通过将要执行的下一个指令的有效地址与分支地址寄存器，循环中的第一条指令的有效地址从分支目标寄存器传递到操作寄存器。

7. 发明申请

US20130227250A1 SIMD ACCELERATOR FOR DATA COMPARISON 审中-公开
标题翻译：用于数据比较的SIMD加速器
公开(公告)号：US20130227250A1
公开(公告)日：2013-08-29
申请号：US13405021
申请日：2012-02-24
申请人： Wilhelm Haller , Ulrich Krauch , Kurt Lind , Friedrich Schroeder , Alexander Woerner
发明人： Wilhelm Haller , Ulrich Krauch , Kurt Lind , Friedrich Schroeder , Alexander Woerner
IPC分类号： G06F9/30 , G06F9/345 , G06F9/302
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/3887
摘要： Some example embodiments include an apparatus for comparing a first operand to a second operand. The apparatus includes a SIMD accelerator configured to compare first multiple parts (e.g., bytes) of first operand to second multiple parts (e.g., bytes) of the second operand. The SIMD accelerator includes a ones' complement subtraction logic and a twos' complement logic configured to perform logic operations on the multiple parts of the first operand and the multiple parts of the second operand to generate a group of carry out and propagate data across bits of the multiple parts. At least a portion of the group of carry out and propagate data is reused in the group of logic operations.
摘要翻译：一些示例性实施例包括用于将第一操作数与第二操作数进行比较的装置。该装置包括配置为将第一操作数的第一多个部分（例如，字节）与第二操作数的第二多个部分（例如，字节）进行比较的SIMD加速器。 SIMD加速器包括一个补码减法逻辑和二进制补码逻辑，其被配置为对第一操作数的多个部分和第二操作数的多个部分执行逻辑运算，以生成一组进位和传播数据多部分。该组执行和传播数据的至少一部分在逻辑操作组中被重用。

8. 发明申请

US20110035712A1 Method and System for Placement of Electronic Circuit Components in Integrated Circuit Design 有权
标题翻译：电子电路元件在集成电路设计中的放置方法与系统
公开(公告)号：US20110035712A1
公开(公告)日：2011-02-10
申请号：US12831306
申请日：2010-07-07
申请人： Elmar Gaugler , Wilhelm Haller , Friedhelm Kessler
发明人： Elmar Gaugler , Wilhelm Haller , Friedhelm Kessler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.
摘要翻译：本发明涉及一种用于将设计单元的多级分级描述宏放置在芯片上的方法和系统。该方法通过将设计单元的宏结构重新分配为一组锁存宏和一组组合宏来开始。根据定义，组合宏被构造成使得它不包含锁存器，并且锁存宏包含锁存器，并且被构造成使得锁存宏的每个主输入/输出与输入或输出的一个锁存在所述锁存宏中。在重新分区宏结构之后，锁存宏在临时边界内合成并放置在芯片上。随后，将组合宏顺序地放置在临时边界内并逐个合成。

9. 发明授权

US07546565B2 Method for comparing two designs of electronic circuits 失效
标题翻译：比较两种电子电路设计的方法
公开(公告)号：US07546565B2
公开(公告)日：2009-06-09
申请号：US11622017
申请日：2007-01-11
申请人： Joachim Fenkes , Wilhelm Haller , Tobias Werner , Alexander Woerner
发明人： Joachim Fenkes , Wilhelm Haller , Tobias Werner , Alexander Woerner
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method implemented as a computer program product for comparing two designs of electronic circuits, wherein the design representations comprise several hierarchically related sheets. The method comprises the steps of (a) identifying corresponding top-sheets of the first hierarchy level in the design versions; (b) generating a list of all sub-sheets for each top-sheet and comparing the lists to identify added, removed and common sheets of the corresponding top-sheets; (c) defining the common sheets as corresponding top-sheets of a next hierarchy level; and (d) repeating steps (a)-(c) until at least one of the top-sheets does not comprise any sub-sheet.
摘要翻译：一种实现为用于比较两种电子电路设计的计算机程序产品的方法，其中设计表示包括几个分层相关的片材。该方法包括以下步骤：（a）在设计版本中识别相应的第一层级的表格; （b）生成每个表格的所有子表的列表，并比较列表以识别相应表格的添加，删除和共同的页面; （c）将普通纸张定义为下一层级的相应的表格; 和（d）重复步骤（a） - （c），直到至少一个顶片不包括任何子片。

10. 发明授权

US07530038B2 Method and placement tool for designing the layout of an electronic circuit 失效
标题翻译：用于设计电子电路布局的方法和放置工具
公开(公告)号：US07530038B2
公开(公告)日：2009-05-05
申请号：US11530038
申请日：2006-09-08
申请人： George D. Gristede , Wilhelm Haller , Friedhelm Kessler , Matthias Klein
发明人： George D. Gristede , Wilhelm Haller , Friedhelm Kessler , Matthias Klein
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： According to the present invention a method for the placement of electronic circuit components is provided that supports design modifications by realizing and maintaining relations between the layouts of the components (i1 to i6). These relations are based on relations between the geometrical shapes represented by the layouts for the components. The invention can be implemented by an interactive layout editor.When a layout or the placement of a layout is changed manually, then the placement of the components that are placed already is changed automatically such that the all the relations between the components are realized or maintained. A parent-child relationship can be defined between components such that when the parent component is changed or moved then only the placement of its children is updated automatically. The prioritisation of relations allows resolving conflicts between conflicting relations.
摘要翻译：根据本发明，提供了一种用于放置电子电路部件的方法，其通过实现和维持部件（i1至i6）的布局之间的关系来支持设计修改。这些关系基于组件布局所表示的几何形状之间的关系。本发明可以通过交互式布局编辑器实现。当布局或布局布局被手动更改时，已经放置的组件的放置自动更改，从而实现或维护组件之间的所有关系。可以在组件之间定义父子关系，以便当父组件更改或移动时，只有子组的位置才能自动更新。关系的优先化允许解决冲突的冲突。

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