会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 1. 发明授权
      US08335878B2 Multiport memory architecture, devices and systems including the same, and methods of using the same 有权
    • Multiport memory architecture, devices and systems including the same, and methods of using the same
    • 多端口存储器架构，包括相同的器件和系统以及使用它们的方法
    • US08335878B2
    • 2012-12-18
    • US12494076
    • 2009-06-29
    • Winston Lee , Sehat Sutardja , Donald Pannell
    • Winston Lee , Sehat Sutardja , Donald Pannell
    • G06F7/00 , G11C11/401
    • G11C7/1075
    • A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.
    • 多端口内存架构，系统包括相同以及使用方法。 架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器 阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。 系统通常包括体现本文公开的一个或多个发明构思的系统。 所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。 本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用 消除FIFO。 本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US07571287B2 Multiport memory architecture, devices and systems including the same, and methods of using the same 有权
    • Multiport memory architecture, devices and systems including the same, and methods of using the same
    • 多端口存储器架构，包括相同的器件和系统以及使用它们的方法
    • US07571287B2
    • 2009-08-04
    • US10702744
    • 2003-11-05
    • Winston Lee , Sehat Sutardja , Donald Pannell
    • Winston Lee , Sehat Sutardja , Donald Pannell
    • G06F12/00
    • G11C7/1075
    • A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses.
    • 多端口内存架构，系统包括相同以及使用方法。 架构通常包括（a）存储器阵列; （b）配置成接收和/或发送数据的多个端口; 以及（c）多个端口缓冲器，每个端口缓冲器被配置为从一个或多个端口发送数据和/或从一个或多个端口接收数据，并且所有端口缓冲器被配置为（i）将数据发送到存储器 阵列在第一公共总线上，（ii）在第二公共总线上从存储器阵列接收数据。 系统通常包括体现本文公开的一个或多个发明构思的系统。 所述方法通常涉及将数据块写入到数据块，从存储器读取数据块和/或传送数据块。 本发明有利地通过将端口缓冲器紧密地耦合到主存储器并且有利地使用存储器读写路径的长段上的点对点通信来减少数据通信中的特别是网络交换机中的等待时间，从而减少路由拥塞和启用 消除FIFO。 本发明有利地缩小芯片尺寸并提供增加的数据传输速率和吞吐量，并且在优选实施例中，存储器读和写总线中的电阻和/或电容减小。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US06947324B1 Logic process DRAM 有权
    • Logic process DRAM
    • 逻辑处理DRAM
    • US06947324B1
    • 2005-09-20
    • US10734060
    • 2003-12-12
    • Winston Lee , Peter Lee , Sehat Sutardja
    • Winston Lee , Peter Lee , Sehat Sutardja
    • G11C7/18 , G11C11/24 , G11C11/4097 , H01L21/8242 , H01L27/02
    • G11C11/4097 , G11C7/18 , H01L27/0207 , H01L27/10885 , Y10S257/908
    • A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.
    • 提供了包括具有提高的信噪比，降低的位线电容和减小的面积的动态随机存取存储器（DRAM）单元的半导体集成电路器件。 DRAM单元包括多个位线对，每个位线对包括第一金属导体和第二金属导体。 每个位线对包括参考位线和感测位线。 每个位线对可以被配置为使得参考位线和感测位线相对于彼此纵向定向。 或者，每个位线对被配置为使得第一金属导体和第二金属导体在至少一个位置上彼此对称地扭曲。 单元板和晶体管栅极之间的横向间隔最小化，导致总面积减小。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US07609538B1 Logic process DRAM 有权
    • Logic process DRAM
    • 逻辑处理DRAM
    • US07609538B1
    • 2009-10-27
    • US11449957
    • 2006-06-09
    • Winston Lee , Peter Lee , Sehat Sutardja
    • Winston Lee , Peter Lee , Sehat Sutardja
    • G11C5/06
    • G11C5/063 , G11C7/02 , G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097 , H01L27/10885
    • A semiconductor integrated circuit device includes a dynamic random access memory (DRAM) unit. The DRAM unit comprises a plurality of bit line pairs. Each bit line pair includes a first bit line and a second bit line. The first bit line and the second bit line within each bit line pair are aligned adjacent to each other. Each of a plurality of word lines is associated with the bit lines such that an array is formed by the bit lines and the associated word lines. Each bit line is associated with both first and second interconnect layers. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of amplifiers is in communication with a first bit line and a second bit line within a bit line pair.
    • 半导体集成电路器件包括动态随机存取存储器（DRAM）单元。 DRAM单元包括多个位线对。 每个位线对包括第一位线和第二位线。 每个位线对内的第一位线和第二位线彼此相邻排列。 多个字线中的每一个与位线相关联，使得阵列由位线和相关联的字线形成。 每个位线都与第一和第二互连层相关联。 多个存储器单元中的每一个与沿着每个字线的每隔一个位线相关联。 多个放大器中的每一个与位线对内的第一位线和第二位线通信。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US07596011B1 Logic process DRAM 失效
    • Logic process DRAM
    • 逻辑处理DRAM
    • US07596011B1
    • 2009-09-29
    • US11710818
    • 2007-02-26
    • Winston Lee , Peter Lee , Sehat Sutardja
    • Winston Lee , Peter Lee , Sehat Sutardja
    • G11C5/06
    • G11C5/063 , G11C7/02 , G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097 , H01L27/10885
    • An integrated circuit device comprises a plurality of bit line pairs. First and second bit lines are aligned with each other in an end-to-end arrangement. The first and second bit lines are arranged consecutively adjacent to one another, respectively. A plurality of word lines is associated with the first bit lines and the second bit lines. A first array includes the first bit lines and first associated ones of the plurality of word lines, and wherein a second array includes the second bit lines and second ones of the plurality of associated word lines. A first plurality of multiplexers communicates with two adjacent bits lines within one of the first and second arrays. The first array operates as a sense array and the second array operates as a reference array when at least one of the plurality of word lines is active in the first array.
    • 集成电路装置包括多个位线对。 第一和第二位线在端对端布置中彼此对准。 第一和第二位线分别彼此相邻布置。 多个字线与第一位线和第二位线相关联。 第一阵列包括第一位线和多个字线中的第一相关联的线，并且其中第二阵列包括第二位线和多个关联字线中的第二位线。 第一多个复用器与第一和第二阵列之一内的两个相邻位线通信。 当第一阵列中的至少一个字线处于活动状态时，第一阵列作为感测阵列工作，而第二阵列作为参考阵列工作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US06680859B1 Logic process DRAM 失效
    • Logic process DRAM
    • 逻辑处理DRAM
    • US06680859B1
    • 2004-01-20
    • US10336423
    • 2003-01-02
    • Winston Lee , Peter Lee , Sehat Sutardja
    • Winston Lee , Peter Lee , Sehat Sutardja
    • G11C700
    • H01L27/10885 , G11C11/4097 , H01L23/5225 , H01L27/0207 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
    • A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.
    • 提供了包括具有提高的信噪比，降低的位线电容和减小的面积的动态随机存取存储器（DRAM）单元的半导体集成电路器件。 DRAM单元包括多个位线对，每个位线对包括第一金属导体和第二金属导体。 每个位线对包括参考位线和感测位线。 每个位线对可以被配置为使得参考位线和感测位线相对于彼此纵向定向。 或者，每个位线对被配置为使得第一金属导体和第二金属导体在至少一个位置上彼此对称地扭曲。 单元板和晶体管栅极之间的横向间隔最小化，导致总面积减小。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US07184290B1 Logic process DRAM 有权
    • Logic process DRAM
    • 逻辑处理DRAM
    • US07184290B1
    • 2007-02-27
    • US11138681
    • 2005-05-27
    • Winston Lee , Peter Lee , Sehat Sutardja
    • Winston Lee , Peter Lee , Sehat Sutardja
    • G11C5/06
    • G11C5/063 , G11C7/02 , G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097 , H01L27/10885
    • A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end arrangement. The first bit lines are arranged substantially parallel and consecutively adjacent to one another. The second bit lines are arranged substantially parallel and consecutively adjacent to one another. Each word line is associated with either the first bit lines or the second bit lines. A first array is formed by the first bit lines and the associated word lines. A second array is formed by the second bit lines and the associated word lines. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays.
    • 动态随机存取存储器（DRAM）单元包括多个位线对和字线。 每个位线对包括在端对端布置中彼此对准的第一和第二位线。 第一位线基本上平行并且彼此相邻地布置。 第二位线基本上平行并且彼此相邻地布置。 每个字线与第一位线或第二位线相关联。 第一阵列由第一位线和相关联的字线形成。 第二阵列由第二位线和相关联的字线形成。 多个存储器单元中的每一个与沿着每个字线的每隔一个位线相关联。 多个复用器中的每一个与第一和第二阵列之一内的两个相邻位线连通。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US06570781B1 Logic process DRAM 有权
    • Logic process DRAM
    • 逻辑处理DRAM
    • US06570781B1
    • 2003-05-27
    • US09881474
    • 2001-06-14
    • Winston Lee , Peter Lee , Sehat Sutardja
    • Winston Lee , Peter Lee , Sehat Sutardja
    • G11C700
    • H01L27/10885 , G11C11/4097 , H01L23/5225 , H01L27/0207 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
    • A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.
    • 提供了包括具有提高的信噪比，降低的位线电容和减小的面积的动态随机存取存储器（DRAM）单元的半导体集成电路器件。 DRAM单元包括多个位线对，每个位线对包括第一金属导体和第二金属导体。 每个位线对包括参考位线和感测位线。 每个位线对可以被配置为使得参考位线和感测位线相对于彼此纵向定向。 或者，每个位线对被配置为使得第一金属导体和第二金属导体在至少一个位置上彼此对称地扭曲。 单元板和晶体管栅极之间的横向间隔最小化，导致总面积减小。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号