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1. 发明授权

US08154326B2 Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit 有权
标题翻译：功率控制电路，电源控制电路的控制方法，电源控制电路的DLL电路
公开(公告)号：US08154326B2
公开(公告)日：2012-04-10
申请号：US12770702
申请日：2010-04-29
申请人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
发明人： Won Joo Yun , Hyun Woo Lee , Dong Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.
摘要翻译：功率控制电路包括：检查单元，接收参考时钟并产生用于循环地激活DLL电路的反馈回路的检查信号;相位检测单元，其检测参考时钟和反馈时钟之间的相位差，并产生相位差检测信号，以及响应于锁定完成信号，检查信号和相位差检测信号产生电力切断信号的信号组合单元。

2. 发明授权

US08085072B2 Semiconductor integrated circuit having delay locked loop circuit 有权
标题翻译：具有延迟锁定环路的半导体集成电路
公开(公告)号：US08085072B2
公开(公告)日：2011-12-27
申请号：US12648380
申请日：2009-12-29
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/095
摘要： A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal.
摘要翻译：提供半导体集成电路。半导体集成电路包括：响应于多个延迟控制信号而将输入时钟信号延迟预定时间的延迟锁定环（DLL）输出块，并提供DLL时钟信号; 锁定控制块，被配置为比较参考时钟信号的相位和反馈时钟信号的相位，并且响应于所述多个延迟控制信号使参考时钟信号的相位和反馈时钟信号的相位同步; 以及锁定检测块，被配置为检测参考时钟信号的相位和反馈时钟信号的相位是否同步，并且DLL时钟信号被锁定，其中，当DLL时钟信号被锁定时，锁定控制块提供通过将输入时钟信号除以n（其中n是等于或大于2的自然数）获得的参考时钟信号作为内部DLL时钟信号。

3. 发明申请

US20110025390A1 UPDATE CONTROL APPARATUS IN DLL CIRCUIT 失效
标题翻译： DLL电路中的更新控制装置
公开(公告)号：US20110025390A1
公开(公告)日：2011-02-03
申请号：US12648516
申请日：2009-12-29
申请人： Won Joo YUN
发明人： Won Joo YUN
IPC分类号： H03L7/18
CPC分类号： H03L7/0814 , H03L7/0816
摘要： An update control apparatus in a DLL circuit is provided. The update control apparatus includes a logic value determination, a phase information collection unit, and an update control unit. The logic value determination unit is configured to determine a logic value of a phase detection signal for a first period interval of a reference clock signal to generate a phase information signal, and configured to extend the first period interval into a second period interval when an extension instruction signal is enabled. The phase information collection unit is configured to determine consecutive logic values of an update possible signal to generate the extension instruction signal, and configured to collect the phase information signal to generate an update information signal. The update control unit is configured to generate the update possible signal, a valid interval signal, and an update control signal in response to the update information signal.
摘要翻译：提供了DLL电路中的更新控制装置。更新控制装置包括逻辑值确定，相位信息收集单元和更新控制单元。逻辑值确定单元被配置为确定参考时钟信号的第一周期间隔的相位检测信号的逻辑值，以生成相位信息信号，并且被配置为当第一周期间隔延长到第二周期间隔时，指令信号被使能。相位信息收集单元被配置为确定更新可能信号的连续逻辑值以生成扩展指令信号，并且被配置为收集相位信息信号以生成更新信息信号。更新控制单元被配置为响应于更新信息信号而产生更新可能信号，有效间隔信号和更新控制信号。

4. 发明申请

US20110025384A1 DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：用于在半导体集成电路中产生时钟的器件
公开(公告)号：US20110025384A1
公开(公告)日：2011-02-03
申请号：US12646608
申请日：2009-12-23
申请人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
IPC分类号： H03L7/06 , G06F1/04
CPC分类号： G06F1/06 , H03L7/0812 , H03L7/0995 , H03L7/16
摘要： Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.
摘要翻译：半导体集成电路的各种实施例。根据一个示例性实施例，半导体集成电路包括被配置为产生多相内部时钟的多相时钟发生器; 第一边缘组合单元，被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第一频率的第一输出时钟，并将所述第一输出时钟发送到第一端口; 以及第二边缘组合单元，其被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第二频率的第二输出时钟，并将所述输出时钟发送到第二端口。

5. 发明申请

US20100289542A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20100289542A1
公开(公告)日：2010-11-18
申请号：US12493804
申请日：2009-06-29
申请人： Won Joo YUN , Hyun Woo LEE , Ki Han KIM
发明人： Won Joo YUN , Hyun Woo LEE , Ki Han KIM
IPC分类号： H03L7/06 , H03K5/04
CPC分类号： H03L7/0814 , H03K5/04 , H03K5/1565
摘要： A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.
摘要翻译：半导体集成电路包括：频率确定单元，被配置为确定半导体集成电路的操作速度并产生频率区域信号; 占空比控制单元，被配置为检测DLL时钟的占空比并产生占空比控制信号; 占空比校正单元，被配置为通过响应于频域信号校正输入时钟的占空比并响应于占空比控制信号来产生校正时钟; 以及被配置为通过控制校正时钟的相位来产生DLL时钟的DLL（延迟锁定环路）。

6. 发明申请

US20100264966A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US20100264966A1
公开(公告)日：2010-10-21
申请号：US12493756
申请日：2009-06-29
申请人： Hyun Woo LEE , Won Joo YUN
发明人： Hyun Woo LEE , Won Joo YUN
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40611 , G11C2211/4067
摘要： A semiconductor integrated circuit includes an update control unit configured to generate an update control signal in response to a first command and a second command; and a DLL (Delay Locked Loop) circuit configured to generate an output clock by controlling a phase of an external clock in response to the update control signal.
摘要翻译：半导体集成电路包括：更新控制单元，被配置为响应于第一命令和第二命令生成更新控制信号; 以及DLL（延迟锁定环路）电路，被配置为通过响应于更新控制信号控制外部时钟的相位而产生输出时钟。

7. 发明授权

US07761757B2 Apparatus and method of setting test mode in semiconductor integrated circuit 有权
标题翻译：设置半导体集成电路测试模式的方法和设备
公开(公告)号：US07761757B2
公开(公告)日：2010-07-20
申请号：US12013866
申请日：2008-01-14
申请人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
发明人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
IPC分类号： G01R31/28
CPC分类号： G11C29/46 , G11C29/14 , G11C2029/0407 , Y10T307/747 , Y10T307/826 , Y10T307/858 , Y10T307/977
摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
摘要翻译：一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值响应于编码控制信号的测试码。

8. 发明授权

US07733147B2 Delay circuit of delay locked loop having single and dual delay lines and control method of the same 有权
标题翻译：具有单延迟线和双延迟线的延迟锁定环路的延迟电路及其控制方法
公开(公告)号：US07733147B2
公开(公告)日：2010-06-08
申请号：US12172887
申请日：2008-07-14
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00052 , H03K2005/00058
摘要： A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.
摘要翻译：延迟锁定环路中的延迟电路包括：第一延迟电路单元，用于响应于第一控制信号使用单个延迟线延迟输入信号，然后输出第一延迟信号和第二延迟信号;以及第二延迟电路单元，使用双延迟线延迟与第二控制信号和第三控制信号对应的延迟时间的第一延迟信号和第二延迟信号，然后输出第三延迟信号和第四延迟信号。

9. 发明申请

US20090174447A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US20090174447A1
公开(公告)日：2009-07-09
申请号：US12176217
申请日：2008-07-18
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0802 , H03L7/087 , H03L7/095
摘要： A semiconductor integrated circuit is disclosed. The disclosed semiconductor integrated circuit of the present invention includes a DLL (Delay Locked Loop) controller that controls whether to activate a DLL at the entry of a power down mode, in response to a result of detecting whether a range of phase change of an external clock signal is within a predetermined range, and a DLL block that provides a result of comparing a reference clock signal with a feedback clock signal to the DLL controller and also provides a delay locked clock signal that is periodically updated, in response to the reference clock signal, under the control of an activated output signal from the DLL controller.
摘要翻译：公开了一种半导体集成电路。所公开的本发明的半导体集成电路包括响应于检测外部的相位变化范围的结果来控制是否在断电模式的入口处激活DLL的DLL（延迟锁定环路）时钟信号在预定范围内，以及DLL块，其将提供将参考时钟信号与反馈时钟信号进行比较的结果提供给DLL控制器，并且还响应于参考时钟提供周期性更新的延迟锁定时钟信号信号，在来自DLL控制器的激活的输出信号的控制下。

10. 发明授权

US07557627B2 Semiconductor memory device for generating a delay locked clock in early stage 有权
标题翻译：用于在早期产生延迟锁定时钟的半导体存储器件
公开(公告)号：US07557627B2
公开(公告)日：2009-07-07
申请号：US11715783
申请日：2007-03-08
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： G11C8/18 , G11C7/22 , G11C7/222 , H03L7/07 , H03L7/0814 , H03L7/095
摘要： A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.
摘要翻译：半导体存储装置包括第一延迟锁定环，其被配置为将系统时钟延迟预定时间，从而产生使数据输出定时与系统时钟同步的第一延迟锁定时钟;第二延迟锁定环，被配置为延迟系统时钟的反相信号系统时钟预定时间，从而产生将数据输出定时与系统时钟同步的第二延迟锁定时钟，以及配置为选择第一和第二延迟锁定时钟之一的时钟选择块，从而作为参考时钟输出数据输出。

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