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1. 发明授权

US11445959B2 Method and apparatus of modulating a neuronal firing frequency at a brain functional site in a brain 有权
公开(公告)号：US11445959B2
公开(公告)日：2022-09-20
申请号：US16113166
申请日：2018-08-27
申请人： Xiaoping Li , Qian Xia , Jessica Li , Joanna Le Xi Li
发明人： Xiaoping Li , Qian Xia , Jessica Li , Joanna Le Xi Li
IPC分类号： A61M21/02 , A61N2/00 , A61B5/245 , A61B5/00 , A61B5/0507 , A61N2/02 , A61M21/00
摘要： The present application provides a method and an apparatus of modulating a neuronal firing frequency at a brain functional site in a brain, the method comprising: generating an electromagnetic field with its power in variation at the preset modulating frequency; and arranging the generated electromagnetic field near the brain such that the brain functional site is within the range of the near field of the electromagnetic field, to polarize extracellular fluid at the brain functional site with the power of the electromagnetic field, such that a polarization density of the extracellular fluid varies at the preset modulating frequency and neurons in the extracellular fluid are modulated to fire at the preset modulating frequency.

2. 发明申请

US20190220856A1 TECHNIQUES FOR CONDUCTING TRANSACTIONS UTILIZING CRYPTOCURRENCY 审中-公开
公开(公告)号：US20190220856A1
公开(公告)日：2019-07-18
申请号：US15870574
申请日：2018-01-12
申请人： Xi Li , Wen Zhao Cheng , Jun Ryan Menorca Tagama , Satrajit Ray , Gabriel Jin Juan Ang , Lavanya Rengarajan
发明人： Xi Li , Wen Zhao Cheng , Jun Ryan Menorca Tagama , Satrajit Ray , Gabriel Jin Juan Ang , Lavanya Rengarajan
IPC分类号： G06Q20/38 , G06Q20/40 , G06Q20/06
CPC分类号： G06Q20/3823 , G06Q20/065 , G06Q20/401 , H04L2209/56
摘要： Embodiments of the invention are directed to systems and methods for conducting a transaction utilizing a cryptocurrency. The user may fund a cryptocurrency account with his pre-existing cryptocurrency. An issuer may purchase cryptocurrency within a cryptocurrency exchange. The user may then utilize a payment device (e.g., a Crypto Debit Card) that is associated with a cryptocurrency balance to conduct a transaction with a merchant for goods and/or services. An authorization request message may be transmitted to the authorizing entity computer. The authorizing entity computer may determine a cryptocurrency amount corresponding to the fiat currency transaction amount of the authorization request message. A sell request message may be transmitted to an exchange that facilitates the sale of the cryptocurrency amount. If the sale is successful, the authorizing entity computer may transmit an authorization response message indicating that the transaction is approved and the merchant may release the purchased goods and/or services.

3. 发明授权

US08947924B2 Data readout circuit of phase change memory 有权
标题翻译：相变存储器的数据读出电路
公开(公告)号：US08947924B2
公开(公告)日：2015-02-03
申请号：US13202963
申请日：2011-06-24
申请人： Xi Li , Houpeng Chen , Zhitang Song , Daolin Cai
发明人： Xi Li , Houpeng Chen , Zhitang Song , Daolin Cai
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0026 , G11C2013/0054
摘要： A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result. Compared with the prior art, the data readout circuit of phase change memory provided by the present invention can effectively enhance the data readout speed, decrease the misreading window between high resistance state and low resistance state, reduce the crosstalk of data readout, and improve the reliability of data readout.
摘要翻译：一种相变存储器的数据读出电路，涉及一个或多个相变存储单元，其中每个相变存储单元通过位线和字线连接到控制电路; 所述数据读出电路包括：钳位电压发生电路，用于产生钳位电压; 预充电电路，用于在钳位电压的控制下快速充电位线; 夹紧电流产生电路，用于产生钳位电流，以在钳位电压的控制下将位线保持在钳位状态; 钳位电流运行电路，用于对钳位电流进行减法和乘法，以增加高电阻状态和低电阻状态之间的钳位电流差; 一个读出放大器电路，用于比较工作钳位电流和参考电流，并输出读出结果。与现有技术相比，本发明提供的相变存储器的数据读出电路可以有效提高数据读出速度，减少高电阻状态和低电阻状态之间的误读窗口，减少数据读出的串扰，数据读出的可靠性。

4. 发明授权

US08455327B2 Trench capacitor with spacer-less fabrication process 失效
公开(公告)号：US08455327B2
公开(公告)日：2013-06-04
申请号：US13198100
申请日：2011-08-04
申请人： Chengwen Pei , Xi Li , Geng Wang
发明人： Chengwen Pei , Xi Li , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L29/0692 , H01L21/3081 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

5. 发明申请

US20120104500A1 SHALLOW TRENCH ISOLATION RECESS REPAIR USING SPACER FORMATION PROCESS 失效
标题翻译：使用间隙形成过程进行浅层分离分离修复
公开(公告)号：US20120104500A1
公开(公告)日：2012-05-03
申请号：US12914095
申请日：2010-10-28
申请人： Ming Cai , Xi Li , Frank D. Tamweber, JR.
发明人： Ming Cai , Xi Li , Frank D. Tamweber, JR.
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823468
摘要： A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.
摘要翻译：形成半导体器件的方法包括在多个晶体管栅极结构上形成间隔层，晶体管栅极结构形成在衬底的有源和浅沟槽隔离（STI）区域上。对间隔层进行定向蚀刻以形成与多个晶体管栅极结构相邻的侧壁间隔物，并且间隔层的水平填充部分保留在STI区域中存在的多个凹部中，以使STI区域基本平坦化在其之后的材料沉积之前。

6. 发明申请

US20110108895A1 METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS 有权
标题翻译：形成不对称间隔的方法和使用不对称间隔制作半导体器件的方法
公开(公告)号：US20110108895A1
公开(公告)日：2011-05-12
申请号：US12983477
申请日：2011-01-03
申请人： Kangguo Cheng , Xi Li , Richard Stephen Wise
发明人： Kangguo Cheng , Xi Li , Richard Stephen Wise
IPC分类号： H01L29/78 , H01L21/3065
CPC分类号： H01L21/67069 , H01J37/32733 , H01J2237/20207 , H01L21/3086 , H01L21/31116 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7835 , H01L29/7848 , H01L29/78654
摘要： A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.
摘要翻译：制造不对称间隔物的方法，使用不对称间隔物制造的结构和用于制造不对称间隔物的装置。该方法包括：在基底上形成具有顶表面和相对的第一和第二侧壁并具有平行于侧壁的纵向轴线的结构; 在所述基底的顶表面，所述结构的顶表面和所述结构的侧壁上形成共形层; 相对于反应离子通量使基板围绕纵向轴线倾斜，反应离子的流量以锐角撞击共形层; 以及将所述共形层暴露于所述反应离子的通量，直到所述共形层从所述结构的顶表面去除并且所述衬底的顶表面在所述第一侧壁上留下第一间隔物，并且在所述第二侧壁上留下第二间隔物，所述第一间隔物比第二间隔物薄。

7. 发明申请

US20100102373A1 TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS 有权
标题翻译：通过自限制过程形成自对准带的TRENCH存储器
公开(公告)号：US20100102373A1
公开(公告)日：2010-04-29
申请号：US12651608
申请日：2010-01-04
申请人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
发明人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L21/32137 , H01L21/76232 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.
摘要翻译：描述半导体结构。该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。还描述了制造半导体结构的方法。该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

8. 发明申请

US20090230471A1 TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS 失效
标题翻译：通过自限制过程形成自对准带的TRENCH存储器
公开(公告)号：US20090230471A1
公开(公告)日：2009-09-17
申请号：US12048263
申请日：2008-03-14
申请人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
发明人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L21/32137 , H01L21/76232 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.
摘要翻译：描述半导体结构。该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。还描述了制造半导体结构的方法。该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

9. 发明授权

US07560360B2 Methods for enhancing trench capacitance and trench capacitor 失效
标题翻译：增加沟槽电容和沟槽电容的方法
公开(公告)号：US07560360B2
公开(公告)日：2009-07-14
申请号：US11468472
申请日：2006-08-30
申请人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
发明人： Kangguo Cheng , David M. Dobuzinsky , Xi Li
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L28/84 , H01L29/66181
摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.
摘要翻译：公开了用于增强沟槽电容的方法和如此形成的沟槽电容器。在一个实施例中，一种方法包括形成沟槽的第一部分; 在第一部分中沉积介电层; 执行包括第一阶段的反应离子蚀刻以蚀刻所述电介质层并在所述沟槽的第一部分的底表面上形成微掩模，以及形成具有粗糙侧壁的所述沟槽的第二部分; 沉积节点电介质; 并用导体填充沟槽。粗糙的侧壁增加沟槽电容，而不增加处理复杂性或成本。

10. 发明申请

US20080173977A1 POST STI TRENCH CAPACITOR 失效
标题翻译： POST STI TRENCH电容器
公开(公告)号：US20080173977A1
公开(公告)日：2008-07-24
申请号：US11624385
申请日：2007-01-18
申请人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
发明人： Anil K. Chinthakindi , Deok-Kee Kim , Xi Li
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L29/66181
摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.
摘要翻译：在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行结构。

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