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1. 发明授权

US07523422B2 Method of fabricating an integrated circuit to improve soft error performance 有权
标题翻译：制造集成电路以提高软错误性能的方法
公开(公告)号：US07523422B2
公开(公告)日：2009-04-21
申请号：US11683278
申请日：2007-03-07
申请人： Xiaowei Zhu , Robert C. Baumann
发明人： Xiaowei Zhu , Robert C. Baumann
IPC分类号： G06F17/50 , H03K19/003
CPC分类号： G06F17/5045 , H01L27/11
摘要： The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.
摘要翻译：本发明在一个方面提供一种设计集成电路的方法。在该特定方面中，该方法包括通过将相对于集成电路的节点的结构定位成与子原子粒子相关联的线性能量转移到节点中来降低集成电路中的软错误风险，使得线性能量传递不超过与集成电路相关联的阈值。

2. 发明申请

US20070157349A1 Method of Fabricating an Integrated Circuit to Improve Soft Error Performance 有权
标题翻译：制造集成电路以提高软错误性能的方法
公开(公告)号：US20070157349A1
公开(公告)日：2007-07-05
申请号：US11683278
申请日：2007-03-07
申请人： Xiaowei Zhu , Robert Baumann
发明人： Xiaowei Zhu , Robert Baumann
IPC分类号： H03K19/00 , H01L23/58 , H01L25/00
CPC分类号： G06F17/5045 , H01L27/11
摘要： The present invention provides, in one aspect, a method of designing an integrated circuit 500. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit 500 by locating a structure 526, 528 relative to a node 516 of the integrated circuit 500 to reduce a linear energy transfer associated with a sub-atomic particle 530, 532 into the node 516, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit 500.
摘要翻译：本发明在一个方面提供一种设计集成电路500的方法。在该特定方面，该方法包括通过相对于集成电路500的节点516定位结构526,528以减少与子原子粒子530,532相关联的线性能量传递来降低集成电路500中的软错误风险进入节点516，使得线性能量传递不超过与集成电路500相关联的阈值。

3. 发明申请

US20060150128A1 Method of fabricating and integrated circuit to improve soft error performance 有权
标题翻译：制造和集成电路的方法，以提高软错误性能
公开(公告)号：US20060150128A1
公开(公告)日：2006-07-06
申请号：US11030273
申请日：2005-01-06
申请人： Xiaowei Zhu , Robert Baumann
发明人： Xiaowei Zhu , Robert Baumann
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H01L27/11
摘要： The present invention provides, in one aspect, a method of designing an integrated circuit 500. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit 500 by locating a structure 526, 528 relative to a node 516 of the integrated circuit 500 to reduce a linear energy transfer associated with a sub-atomic particle 530, 532 into the node 516, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit 500.
摘要翻译：本发明在一个方面提供一种设计集成电路500的方法。在该特定方面，该方法包括通过相对于集成电路500的节点516定位结构526,528以减少与子原子粒子530,532相关联的线性能量传递来降低集成电路500中的软错误风险进入节点516，使得线性能量传递不超过与集成电路500相关联的阈值。

4. 发明申请

US20140012603A1 CAPACITY PLANNING AND MODELING FOR OPTIMIZATION OF TASK OUTCOMES 审中-公开
标题翻译：能力规划和优化任务成果的建模
公开(公告)号：US20140012603A1
公开(公告)日：2014-01-09
申请号：US13544408
申请日：2012-07-09
申请人： James Scanlon , Premnath Ayyalasomayajula , Xiaowei Zhu
发明人： James Scanlon , Premnath Ayyalasomayajula , Xiaowei Zhu
IPC分类号： G06Q10/06 , G06Q40/08
CPC分类号： G06Q10/0631
摘要： Systems and methods for optimizing outcomes in view of various business scenarios are based on a unique quantification of work and estimate of task duration, which may be used to develop a measure of the work required to complete a task. This measure may be compared to forecasted work and used to allocate resources accordingly. Additionally, optimal outcomes may be identified subject to any classification, such as by class of worker, type of task, location of task, and/or size of work unit.
摘要翻译：鉴于各种业务场景，优化成果的系统和方法基于工作的独特量化和任务持续时间的估计，可用于开发完成任务所需工作的度量。这个措施可以与预测的工作进行比较，并用于相应地分配资源。另外，可以根据任何分类来确定最佳结果，例如按工人类别，任务类型，任务位置和/或工作单位的大小。

5. 发明申请

US20100157642A1 MITIGATION OF CHARGE SHARING IN MEMORY DEVICES 有权
标题翻译：存储设备中的充电分配缓解
公开(公告)号：US20100157642A1
公开(公告)日：2010-06-24
申请号：US12338393
申请日：2008-12-18
申请人： Xiaowei Zhu , Xiaowei Deng
发明人： Xiaowei Zhu , Xiaowei Deng
IPC分类号： G11C5/02 , G11C11/56
CPC分类号： G11C5/005 , G11C11/412 , G11C2211/4013
摘要： One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.
摘要翻译：一个实施例涉及设置在基板上的存储元件。存储元件包括适于协同地存储相同数据的第一和第二互锁数据存储元件。第一数据存储元件的输出耦合到第二数据存储元件的输入节点。第二数据存储元件的输出耦合到第一数据存储元件的输入。衬底中的隔离元件横向布置在第一和第二数据存储元件的存储节点之间。隔离元件布置成限制第一和第二数据存储元件的存储节点之间的电荷共享。还公开了其它方法和系统。

6. 发明授权

US07234121B2 Method of fabricating an integrated circuit to improve soft error performance 有权
标题翻译：制造集成电路以提高软错误性能的方法
公开(公告)号：US07234121B2
公开(公告)日：2007-06-19
申请号：US11030273
申请日：2005-01-06
申请人： Xiaowei Zhu , Robert C. Baumann
发明人： Xiaowei Zhu , Robert C. Baumann
IPC分类号： G06F17/50 , H03K19/003
CPC分类号： G06F17/5045 , H01L27/11
摘要： The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.
摘要翻译：本发明在一个方面提供一种设计集成电路的方法。在该特定方面中，该方法包括通过将相对于集成电路的节点的结构定位成与子原子粒子相关联的线性能量转移到节点中来降低集成电路中的软错误风险，使得线性能量传递不超过与集成电路相关联的阈值。

7. 发明申请

US20060031733A1 Power-saving retention mode 审中-公开
标题翻译：省电保留模式
公开(公告)号：US20060031733A1
公开(公告)日：2006-02-09
申请号：US10910440
申请日：2004-08-03
申请人： Xiaowei Zhu , Claude Cirba
发明人： Xiaowei Zhu , Claude Cirba
IPC分类号： G01R31/30 , G06F11/00
CPC分类号： G01R31/318575
摘要： Embodiments of the invention are disclosed wherein methods and systems are provided for implementing a power-saving retention mode in an integrated circuit having both logic elements and memory elements. The methods of the invention include steps for scanning at least some of the logic elements of the integrated circuit and writing the states of the scanned logic elements to memory elements. Upon entering a retention mode, the scanned logic elements of the integrated circuit are powered down to conserve power. Transitioning from retention mode to active mode, the logic elements of the integrated circuit are again powered up and the scanned logic states are restored to the logic elements from the memory elements. Also disclosed is the implementation of the invention in combination with known power-saving techniques.
摘要翻译：公开了本发明的实施例，其中提供了用于在具有逻辑元件和存储元件的集成电路中实现节电保持模式的方法和系统。本发明的方法包括用于扫描集成电路的至少一些逻辑元件并将扫描的逻辑元件的状态写入存储器元件的步骤。进入保持模式时，集成电路的扫描逻辑元件掉电以节省功耗。从保持模式转换到主动模式，集成电路的逻辑元件再次通电，扫描的逻辑状态从存储器元件恢复到逻辑元件。还公开了结合已知的省电技术的本发明的实现。

8. 发明申请

US20050138482A1 Method and apparatus for reducing soft errors 失效
标题翻译：减少软错误的方法和装置
公开(公告)号：US20050138482A1
公开(公告)日：2005-06-23
申请号：US10743165
申请日：2003-12-22
申请人： Norbert Seifert , Xiaowei Zhu
发明人： Norbert Seifert , Xiaowei Zhu
IPC分类号： G11C11/41 , G06F20060101 , G06F11/36 , G11C20060101 , G11C5/00 , G11C11/412 , H03K3/013 , H03K3/037 , G06F11/00
CPC分类号： G11C11/4125
摘要： A method and apparatus for reducing soft errors is disclosed. In some embodiments the method comprises: assigning a plurality of nodes within a storage circuit to a predetermined state; evaluating a plurality of signals coupled to the storage circuit, where evaluating the plurality of signals enables a first node to change from its predetermined state and enables a second node to be more susceptible to perturbations; and maintaining the second node in its predetermined state for a predetermined period of time, where maintaining the predetermined state reduces the storage circuit's susceptibility to soft errors.
摘要翻译：公开了一种减少软错误的方法和装置。在一些实施例中，该方法包括：将存储电路内的多个节点分配到预定状态; 评估耦合到所述存储电路的多个信号，其中评估所述多个信号使得第一节点能够从其预定状态改变，并且使得第二节点更易于扰动; 并且将所述第二节点保持在其预定状态一段预定的时间段，其中保持所述预定状态降低了所述存储电路对软错误的敏感性。

9. 发明申请

US20130262473A1 SYSTEMS, METHODS, AND APPARATUS FOR REVIEWING FILE MANAGEMENT 有权
标题翻译：用于审查文件管理的系统，方法和装置
公开(公告)号：US20130262473A1
公开(公告)日：2013-10-03
申请号：US13431941
申请日：2012-03-27
申请人： James T. Scanlon , Xiaowei Zhu , Maryann Godbout , Song Chen
发明人： James T. Scanlon , Xiaowei Zhu , Maryann Godbout , Song Chen
IPC分类号： G06F17/30
CPC分类号： G06Q40/02 , G06Q40/025
摘要： Systems, apparatus, methods and articles of manufacture provide for reviewing the management of one or more business files. According to some embodiments, methods may include determining a plurality of file review criteria, determining a plurality of file review questions, determining a respective maximum potential review score for each file review question, determining respective responses for the file review questions, adjusting (if necessary) one or more of the maximum potential review scores, and/or determining at least one review score for each file review question answered. Some embodiments may provide for determining a respective review score for a file for each of one or more predetermined file review criteria.
摘要翻译：系统，装置，方法和制品提供审查一个或多个商业文件的管理。根据一些实施例，方法可以包括确定多个文件审查标准，确定多个文件审查问题，确定每个文件审查问题的相应最大潜在审查分数，确定文件审阅问题的相应响应，如果需要）一个或多个最大潜在审查分数，和/或确定每个文件审查问题的至少一个审查分数被回答。一些实施例可以提供为一个或多个预定文件审查标准中的每一个确定文件的相应评审分数。

10. 发明授权

US07855907B2 Mitigation of charge sharing in memory devices 有权
标题翻译：缓解内存设备中的电荷共享
公开(公告)号：US07855907B2
公开(公告)日：2010-12-21
申请号：US12338393
申请日：2008-12-18
申请人： Xiaowei Zhu , Xiaowei Deng
发明人： Xiaowei Zhu , Xiaowei Deng
IPC分类号： G11C5/02
CPC分类号： G11C5/005 , G11C11/412 , G11C2211/4013
摘要： One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.
摘要翻译：一个实施例涉及设置在基板上的存储元件。存储元件包括适于协同地存储相同数据的第一和第二互锁数据存储元件。第一数据存储元件的输出耦合到第二数据存储元件的输入节点。第二数据存储元件的输出耦合到第一数据存储元件的输入。衬底中的隔离元件横向布置在第一和第二数据存储元件的存储节点之间。隔离元件布置成限制第一和第二数据存储元件的存储节点之间的电荷共享。还公开了其它方法和系统。

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