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    • 5. 发明申请
    • MITIGATION OF CHARGE SHARING IN MEMORY DEVICES
    • 存储设备中的充电分配缓解
    • US20100157642A1
    • 2010-06-24
    • US12338393
    • 2008-12-18
    • Xiaowei ZhuXiaowei Deng
    • Xiaowei ZhuXiaowei Deng
    • G11C5/02G11C11/56
    • G11C5/005G11C11/412G11C2211/4013
    • One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.
    • 一个实施例涉及设置在基板上的存储元件。 存储元件包括适于协同地存储相同数据的第一和第二互锁数据存储元件。 第一数据存储元件的输出耦合到第二数据存储元件的输入节点。 第二数据存储元件的输出耦合到第一数据存储元件的输入。 衬底中的隔离元件横向布置在第一和第二数据存储元件的存储节点之间。 隔离元件布置成限制第一和第二数据存储元件的存储节点之间的电荷共享。 还公开了其它方法和系统。
    • 7. 发明申请
    • Power-saving retention mode
    • 省电保留模式
    • US20060031733A1
    • 2006-02-09
    • US10910440
    • 2004-08-03
    • Xiaowei ZhuClaude Cirba
    • Xiaowei ZhuClaude Cirba
    • G01R31/30G06F11/00
    • G01R31/318575
    • Embodiments of the invention are disclosed wherein methods and systems are provided for implementing a power-saving retention mode in an integrated circuit having both logic elements and memory elements. The methods of the invention include steps for scanning at least some of the logic elements of the integrated circuit and writing the states of the scanned logic elements to memory elements. Upon entering a retention mode, the scanned logic elements of the integrated circuit are powered down to conserve power. Transitioning from retention mode to active mode, the logic elements of the integrated circuit are again powered up and the scanned logic states are restored to the logic elements from the memory elements. Also disclosed is the implementation of the invention in combination with known power-saving techniques.
    • 公开了本发明的实施例,其中提供了用于在具有逻辑元件和存储元件的集成电路中实现节电保持模式的方法和系统。 本发明的方法包括用于扫描集成电路的至少一些逻辑元件并将扫描的逻辑元件的状态写入存储器元件的步骤。 进入保持模式时,集成电路的扫描逻辑元件掉电以节省功耗。 从保持模式转换到主动模式,集成电路的逻辑元件再次通电,扫描的逻辑状态从存储器元件恢复到逻辑元件。 还公开了结合已知的省电技术的本发明的实现。
    • 10. 发明授权
    • Mitigation of charge sharing in memory devices
    • 缓解内存设备中的电荷共享
    • US07855907B2
    • 2010-12-21
    • US12338393
    • 2008-12-18
    • Xiaowei ZhuXiaowei Deng
    • Xiaowei ZhuXiaowei Deng
    • G11C5/02
    • G11C5/005G11C11/412G11C2211/4013
    • One embodiment relates to a memory element disposed on a substrate. The memory element includes first and second interlocked data storage elements adapted to cooperatively store the same datum. An output of the first data storage element is coupled to an input node of the second data storage element. An output of the second data storage element is coupled to an input of the first data storage element. An isolation element in the substrate is arranged laterally between storage nodes of the first and second data storage elements. The isolation element is arranged to limit charge sharing between the storage nodes of the first and second data storage elements. Other methods and systems are also disclosed.
    • 一个实施例涉及设置在基板上的存储元件。 存储元件包括适于协同地存储相同数据的第一和第二互锁数据存储元件。 第一数据存储元件的输出耦合到第二数据存储元件的输入节点。 第二数据存储元件的输出耦合到第一数据存储元件的输入。 衬底中的隔离元件横向布置在第一和第二数据存储元件的存储节点之间。 隔离元件布置成限制第一和第二数据存储元件的存储节点之间的电荷共享。 还公开了其它方法和系统。