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1. 发明申请

US20140243501A1 HISTONE DEACETYLASE INHIBITORS AND SYNTHETIC METHOD THEREOF AND USE THEREOF IN MANUFACTURE OF MEDICAMENTS 有权
标题翻译：组胺脱乙酰酶抑制剂及其合成方法及其在制药中的应用
公开(公告)号：US20140243501A1
公开(公告)日：2014-08-28
申请号：US13980308
申请日：2012-02-23
申请人： Sheng Jiang , Shang Li , Zhiyi Yao , Yiwu Yao , Feng Zhang , Yang Chao , Hai Ye , Min Chen
发明人： Sheng Jiang , Shang Li , Zhiyi Yao , Yiwu Yao , Feng Zhang , Yang Chao , Hai Ye , Min Chen
IPC分类号： C07K5/097
CPC分类号： C07K5/0821 , A61K38/06 , C07F7/10 , C07F7/1804 , Y02A50/411
摘要： The invention provides histone deacetylase (HDAC) inhibitors shown as Formula I, where R1 to R8 are as defined in the specification. The invention also provides methods for synthesis of these compounds and applications of these compounds in preparing pharmaceuticals for preventing or treating mammal diseases related to the dysregulation of HDAC.
摘要翻译：本发明提供如式I所示的组蛋白脱乙酰酶（HDAC）抑制剂，其中R1至R8如说明书中所定义。本发明还提供了这些化合物的合成方法和这些化合物在制备用于预防或治疗与HDAC失调相关的哺乳动物疾病的药物中的应用。

2. 再颁专利

USRE43761E1 Jitter measuring method and device 有权
标题翻译：抖动测量方法和装置
公开(公告)号：USRE43761E1
公开(公告)日：2012-10-23
申请号：US12727113
申请日：2010-03-18
申请人： Ming-Yang Chao , Szu-Shan Lo
发明人： Ming-Yang Chao , Szu-Shan Lo
IPC分类号： H04B17/00
CPC分类号： G01R29/26 , H04L1/205
摘要： A jitter measuring method and device, which is capable of measuring jitters in serial digital signal without high-frequency reference clock. The jitter measuring device comprises a rough length measuring unit for measuring rough length for each pulse of the serial digital signal according to a reference clock, and a phase error measuring unit for measuring the phase errors between the edges of the reference clock and the serial digital signal by multi-phase clocks, which are generated by a multi-phase generator according to the reference clock. The jitter measuring device computes the precise length according to the rough length and the phase error, and measures the jitters from the precise length by filters.
摘要翻译：一种抖动测量方法和装置，能够测量串行数字信号中的抖动，无需高频参考时钟。抖动测量装置包括：粗长度测量单元，用于根据参考时钟测量串行数字信号的每个脉冲的粗略长度;以及相位误差测量单元，用于测量参考时钟的边缘与串行数字信号的边沿之间的相位误差信号由多相位时钟产生，由多相发生器根据参考时钟产生。抖动测量装置根据粗长度和相位误差计算精确长度，并通过滤波器从精确长度测量抖动。

3. 发明授权

US07480744B2 Method and apparatus for one time programming 有权
标题翻译：一次编程的方法和装置
公开(公告)号：US07480744B2
公开(公告)日：2009-01-20
申请号：US11563236
申请日：2006-11-27
申请人： Ming-Yang Chao , You-Wen Chang , Chien-Hsun Tung
发明人： Ming-Yang Chao , You-Wen Chang , Chien-Hsun Tung
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G11C17/18 , G06F7/725 , G06F21/57 , G11B20/00086 , G11B2220/213 , G11B2220/2562 , G11C7/24 , H04L9/3066 , H04L2209/12
摘要： A programmable system for storage of one-time programmable information comprises an interface translator and a one-time programmable device. The interface translator receives and translates a command code to program code comprising a sequence of write instructions and a designated data block. The one-time programmable device is coupled to the interface translator, programmed by the write instructions to store the designated data block. The one-time programmable device can only be programmed once, such that the designated data block being stored is fully protected.
摘要翻译：用于存储一次性可编程信息的可编程系统包括接口转换器和一次性可编程器件。接口转换器接收并将命令代码转换成包括写指令序列和指定数据块的程序代码。一次性可编程器件耦合到接口转换器，由写指令编程以存储指定的数据块。一次性可编程设备只能被编程一次，使得存储的指定数据块得到完全保护。

4. 发明申请

US20090013192A1 INTEGRITY CHECK METHOD APPLIED TO ELECTRONIC DEVICE, AND RELATED CIRCUIT 审中-公开
标题翻译：适用于电子设备的完整性检查方法及相关电路
公开(公告)号：US20090013192A1
公开(公告)日：2009-01-08
申请号：US11772829
申请日：2007-07-03
申请人： Ping-Sheng Chen , Ming-Yang Chao , Chi-Chun Hsu , Yao-Dun Chang , Tse-Hong Wu
发明人： Ping-Sheng Chen , Ming-Yang Chao , Chi-Chun Hsu , Yao-Dun Chang , Tse-Hong Wu
IPC分类号： G06F12/14
CPC分类号： G06F11/1004
摘要： An integrity check method applied to an electronic device includes: fetching at least one portion of external data into a specific memory, where the external data is stored within the electronic device; during fetching the portion of the external data into the specific memory, checking whether the size of the fetched data in the specific memory reaches a predetermined value, where the predetermined value is less than the total size of the external data; and when the size of the fetched data in the specific memory reaches the predetermined value, enabling an integrity check of the fetched data.
摘要翻译：应用于电子设备的完整性检查方法包括：将外部数据的至少一部分取出到特定存储器中，其中外部数据存储在电子设备内; 在将外部数据的一部分取入特定存储器期间，检查特定存储器中的获取的数据的大小是否达到预定值，其中预定值小于外部数据的总大小; 并且当特定存储器中的获取的数据的大小达到预定值时，能够对获取的数据进行完整性检查。

5. 发明授权

US07397396B2 Modulation methods and systems 有权
标题翻译：调制方法和系统
公开(公告)号：US07397396B2
公开(公告)日：2008-07-08
申请号：US11550420
申请日：2006-10-18
申请人： Hsin-Cheng Chen , Pi-Hai Liu , Ming-Yang Chao
发明人： Hsin-Cheng Chen , Pi-Hai Liu , Ming-Yang Chao
IPC分类号： H03M5/00
CPC分类号： G11B20/1426 , G11B2020/1288 , G11B2020/1442 , G11B2020/1453 , G11B2020/1457 , G11B2220/2541 , G11B2220/2579
摘要： A modulation system includes an encoder for transferring data words to tentative code words. A DSV control bit generator determines the value of a DSV control bit according to the data words or the tentative code words to optimize the cumulative DSVs corresponding tentative code words, wherein the DSV control bit generator determines the value of a current DSV control bit when at least a subsequent DSV control bit is detected. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.
摘要翻译：调制系统包括用于将数据字传送到临时码字的编码器。 DSV控制位发生器根据数据字或暂定码字来确定DSV控制位的值，以优化对应的暂定码字的累积DSV，其中DSV控制位发生器确定当当前DSV控制位的值在至少检测到随后的DSV控制位。最终码字发生器根据确定的DSV控制位和暂定码字产生最终码字。

6. 发明申请

US20080126753A1 EMBEDDED SYSTEM AND OPERATING METHOD THEREOF 审中-公开
标题翻译：嵌入式系统及其操作方法
公开(公告)号：US20080126753A1
公开(公告)日：2008-05-29
申请号：US11534811
申请日：2006-09-25
申请人： Ming-Yang Chao , Chien-Hsun Tung , Pao-Ching Tseng , Ching Yi Wu
发明人： Ming-Yang Chao , Chien-Hsun Tung , Pao-Ching Tseng , Ching Yi Wu
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3879 , G06F9/3802
摘要： An embedded system and an operating method thereof are disclosed. The embedded system comprises a micro-processor and a co-processor. The co-processor can only process non-interruptible instructions. The micro-processor is powered by an operating system to control the embedded system. When a task requires execution, the micro-processor appoints the co-processor to execute at least one batch command block. The batch command block is compiled with a sequence of non-interruptible instructions. When the task is complete, the co-processor outputs a response signal to the micro-processor.
摘要翻译：公开了嵌入式系统及其操作方法。嵌入式系统包括微处理器和协处理器。协处理器只能处理不可中断的指令。微处理器由操作系统供电以控制嵌入式系统。当任务需要执行时，微处理器指定协处理器执行至少一个批处理命令块。批处理命令块使用一系列不可中断指令进行编译。当任务完成时，协处理器向微处理器输出响应信号。

7. 发明申请

US20070076552A1 Parameter updating methods and systems for optical disc accessing 审中-公开
标题翻译：用于光盘访问的参数更新方法和系统
公开(公告)号：US20070076552A1
公开(公告)日：2007-04-05
申请号：US11243066
申请日：2005-10-04
申请人： Ming-Yang Chao , Chih-Ching Chen
发明人： Ming-Yang Chao , Chih-Ching Chen
IPC分类号： G11B27/36
CPC分类号： G11B27/24 , G11B7/00456
摘要： Methods and systems for dynamically updating velocity dependent parameters during optical disc accessing are provided. A velocity estimator estimates a current velocity of a rotating disc. A storage unit stores a plurality set of parameters, each set corresponds to a preset velocity, and a register stores velocity dependent parameters that are currently used for data recording. A batch controller retrieves a set of parameters from the storage unit according to the current velocity estimated by the velocity estimator, and updates the velocity dependent parameter stored in the register using the parameters retrieved from the storage unit.
摘要翻译：提供了在光盘访问期间动态更新速度相关参数的方法和系统。速度估计器估计旋转盘的当前速度。存储单元存储多组参数，每组参数对应于预设速度，并且寄存器存储当前用于数据记录的速度相关参数。批量控制器根据由速度估计器估计的当前速度从存储单元检索一组参数，并且使用从存储单元检索的参数更新存储在寄存器中的速度相关参数。

8. 发明申请

US20060020527A1 Scalable asset visibility management system 审中-公开
标题翻译：可扩展资产可见性管理系统
公开(公告)号：US20060020527A1
公开(公告)日：2006-01-26
申请号：US10912368
申请日：2004-07-26
申请人： Mohsin Bhally , Jurgen Reinold , Jethender Aitipamula , Yang Chao , Kathy Downie , Samuel Levenson
发明人： Mohsin Bhally , Jurgen Reinold , Jethender Aitipamula , Yang Chao , Kathy Downie , Samuel Levenson
IPC分类号： G06Q40/00
CPC分类号： G06Q10/06 , G06Q40/00
摘要： An asset visibility management system that comprises a common sytem backbone, an asset transaction system interface, and an asset data acquisition and communication device interface. The asset transaction system interface provides communications between the common system backbone and one of a plurality of asset transaction systems. The asset data acquisition and communication device interface provides communication between the common system backbone and a plurality of data acquisition and communication devices. Each of the data acquisition and communication devices are assigned to predefined categories. The predefined categories may include a substantially continuous location category, a substantially non-continuous location category, an identification category, a sensor category, and a time stamp category.
摘要翻译：资产可见度管理系统，包括通用系统骨干，资产交易系统接口，资产数据采集和通信设备接口。资产交易系统接口提供公共系统骨干网和多个资产交易系统之一之间的通信。资产数据采集和通信设备接口提供公共系统骨干网与多个数据采集和通信设备之间的通信。数据采集和通信设备中的每一个被分配给预定类别。预定义的类别可以包括基本上连续的位置类别，基本上非连续的位置类别，识别类别，传感器类别和时间戳类别。

9. 发明授权

US08933195B2 Histone deacetylase inhibitors and synthetic method thereof and use thereof in manufacture of medicaments 有权
标题翻译：组蛋白脱乙酰酶抑制剂及其合成方法及其在药物制造中的应用
公开(公告)号：US08933195B2
公开(公告)日：2015-01-13
申请号：US13980308
申请日：2012-02-23
申请人： Sheng Jiang , Shang Li , Zhiyi Yao , Yiwu Yao , Feng Zhang , Yang Chao , Hai Ye , Min Chen
发明人： Sheng Jiang , Shang Li , Zhiyi Yao , Yiwu Yao , Feng Zhang , Yang Chao , Hai Ye , Min Chen
IPC分类号： C07K5/097 , C07F7/10 , C07F7/18 , A61K38/06
CPC分类号： C07K5/0821 , A61K38/06 , C07F7/10 , C07F7/1804 , Y02A50/411
摘要： The invention provides histone deacetylase (HDAC) inhibitors shown as Formula I, where R1 to R8 are as defined in the specification. The invention also provides methods for synthesis of these compounds and applications of these compounds in preparing pharmaceuticals for preventing or treating mammal diseases related to the dysregulation of HDAC.
摘要翻译：本发明提供如式I所示的组蛋白脱乙酰酶（HDAC）抑制剂，其中R1至R8如说明书中所定义。本发明还提供了这些化合物的合成方法和这些化合物在制备用于预防或治疗与HDAC失调相关的哺乳动物疾病的药物中的应用。

10. 再颁专利

USRE41195E1 Jitter measuring method and device 有权
标题翻译：抖动测量方法和装置
公开(公告)号：USRE41195E1
公开(公告)日：2010-04-06
申请号：US11599634
申请日：2006-11-15
申请人： Ming-Yang Chao , Szu-Shan Lo
发明人： Ming-Yang Chao , Szu-Shan Lo
IPC分类号： H04B17/00
CPC分类号： G01R29/26 , H04L1/205
摘要： A jitter measuring method and device, which is capable of measuring jitters in serial digital signal without high-frequency reference clock. The jitter measuring device comprises a rough length measuring unit for measuring rough length for each pulse of the serial digital signal according to a reference clock, and a phase error measuring unit for measuring the phase errors between the edges of the reference clock and the serial digital signal by multi-phase clocks, which are generated by a multi-phase generator according to the reference clock. The jitter measuring device computes the precise length according to the rough length and the phase error, and measures the jitters from the precise length by filters.
摘要翻译：一种抖动测量方法和装置，能够测量串行数字信号中的抖动，无需高频参考时钟。抖动测量装置包括：粗长度测量单元，用于根据参考时钟测量串行数字信号的每个脉冲的粗略长度;以及相位误差测量单元，用于测量参考时钟的边缘与串行数字信号的边沿之间的相位误差信号由多相位时钟产生，由多相发生器根据参考时钟产生。抖动测量装置根据粗长度和相位误差计算精确长度，并通过滤波器从精确长度测量抖动。

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