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1. 发明申请

US20130214810A1 METHOD FOR TESTING DENSITY AND LOCATION OF GATE DIELECTRIC LAYER TRAP OF SEMICONDUCTOR DEVICE 有权
标题翻译：测试半导体器件栅极电介质层的密度和位置的方法
公开(公告)号：US20130214810A1
公开(公告)日：2013-08-22
申请号：US13879967
申请日：2012-02-28
申请人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
发明人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
IPC分类号： G01R31/26
CPC分类号： G01R31/2642 , G01R31/2621 , H01L22/14 , H01L22/34
摘要： Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.
摘要翻译：提出了一种用于测试半导体器件的栅介质层陷阱的密度和位置的方法。测试方法使用由泄漏路径产生的栅极泄漏电流来测试具有小面积（有效沟道面积小于0.5平方微米）的半导体器件的栅极介电层中的阱密度和二维陷阱位置。本发明特别适用于测试具有超小面积（有效通道面积小于0.05平方微米）的器件。在不同材料和不同工艺的情况下，本方法可以获得栅极电介质层的陷阱分布情况。在本方法中，器件要求简单，测试结构简单，测试成本低，测试快速，可在短时间内获得器件栅极电介质层的陷阱分布，适合用于大批量的自动测试，特别适用于超小型半导体器件制造过程中的过程监控和成品质量检测。

2. 发明申请

US20120241712A1 Resistive-Switching Memory and Fabrication Method Thereof 有权
标题翻译：电阻式开关存储器及其制作方法
公开(公告)号：US20120241712A1
公开(公告)日：2012-09-27
申请号：US13254570
申请日：2011-04-12
申请人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
发明人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.
摘要翻译：本发明公开了一种电阻式开关存储器及其制造方法。电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部电极为板状。底部电极的峰值结构降低了器件的功耗。其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。整个制造工艺简单，可以实现高集成度的装置。

3. 发明申请

US20120181584A1 Resistive Field Effect Transistor Having an Ultra-Steep Subthreshold Slope and Method for Fabricating the Same 审中-公开
标题翻译：具有超陡亚阈值斜率的电阻场效应晶体管及其制造方法
公开(公告)号：US20120181584A1
公开(公告)日：2012-07-19
申请号：US13318329
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/435
摘要： The invention discloses a resistive field effect transistor (ReFET) having an ultra-steep subthreshold slope, which relates to a field of field-effect-transistor logic device and circuit in CMOS ultra-large-scale-integrated circuit (ULSI). The resistive field effect transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a doped source region and a doped drain region, wherein the control gate is configured to adopt a stacked gate structure in which a bottom layer or a bottom electrode layer, a middle layer or a resistive material layer, and a top layer or a top electrode layer are sequentially formed. Compared with the existing methods for breaking the conventional subthreshold slope limititation, the device of the invention has a larger on-current, a lower operation voltage, and a better subthreshold feature.
摘要翻译：本发明公开了一种具有超陡亚阈值斜率的电阻场效应晶体管（ReFET），其涉及CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件和电路的场。电阻场效应晶体管包括控制栅极电极层，栅极电介质层，半导体衬底，掺杂源极区域和掺杂漏极区域，其中控制栅极被配置为采用堆叠栅极结构，其中底层或顺序地形成底部电极层，中间层或电阻材料层，顶层或顶部电极层。与现有的破坏常规阈值斜率限制的方法相比，本发明的器件具有较大的导通电流，较低的工作电压和更好的亚阈值特性。

4. 发明申请

US20050287760A1 Method for fabricating high aspect ratio MEMS device with integrated circuit on the same substrate using post-CMOS process 失效
标题翻译：使用后CMOS工艺在同一衬底上制造具有集成电路的高纵横比MEMS器件的方法
公开(公告)号：US20050287760A1
公开(公告)日：2005-12-29
申请号：US11111344
申请日：2005-04-22
申请人： Guizhen Yan , Yong Zhu , Jie Fan , Xuesong Liu , Jian Zhou , Yangyuan Wang
发明人： Guizhen Yan , Yong Zhu , Jie Fan , Xuesong Liu , Jian Zhou , Yangyuan Wang
IPC分类号： H01L21/4763 , H01L21/76
CPC分类号： B81C1/00246 , B81C2203/0728 , H01L27/0617
摘要： The invention discloses a novel flexible, modular fabrication method for integrated high aspect ratio single crystal silicon microstructures designed and manufactured in a post conventional CMOS process (Post-CMOS). The method involves the standard circuits formation, the electrical isolation trenched etching and refilling, backside etching, interconnection formation, and structure releasing. Further, a method of tailoring the trench profile for refill the trench fully without void is also disclosed.
摘要翻译：本发明公开了一种用于在后常规CMOS工艺（后CMOS）中设计和制造的集成高宽比单晶硅微结构的新颖的柔性，模块化制造方法。该方法包括标准电路形成，电隔离沟槽蚀刻和再填充，背面蚀刻，互连形成和结构释放。此外，还公开了一种调整沟槽轮廓以在没有空隙的情况下完全填充沟槽的方法。

5. 发明授权

US08921174B2 Method for fabricating complementary tunneling field effect transistor based on standard CMOS IC process 有权
标题翻译：基于标准CMOS IC工艺制造互补隧道场效应晶体管的方法
公开(公告)号：US08921174B2
公开(公告)日：2014-12-30
申请号：US13884095
申请日：2012-06-14
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/739
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/823814 , H01L29/66356 , H01L29/7391
摘要： Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.
摘要翻译：本文公开了一种用于制造基于标准CMOS IC工艺的互补隧道场效应晶体管的方法，其属于超大规模集成（ULSI）电路中的场效应晶体管的逻辑器件和电路领域。在该方法中，TFET的本征通道和体区通过在标准CMOS IC工艺中的互补P阱和N阱掩模形成，以形成阱掺杂，沟道掺杂和通过注入进行阈值调整。此外，可以通过布局上的栅极和漏极之间的距离来抑制TFET中的双极效应，从而形成互补的TFET。在根据本发明的方法中，互补隧穿场效应晶体管（TFET）可以通过标准CMOS IC工艺中的现有工艺制造而无需任何附加的掩模和工艺步骤。

6. 发明授权

US08895980B2 Tunneling current amplification transistor 有权
标题翻译：隧道电流放大晶体管
公开(公告)号：US08895980B2
公开(公告)日：2014-11-25
申请号：US13255087
申请日：2011-05-26
申请人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
发明人： Ru Huang , Zhan Zhan , Qianqian Huang , Yangyuan Wang
IPC分类号： H01L29/73 , H01L29/739 , H01L29/00
CPC分类号： H01L29/7391
摘要： The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.
摘要翻译：本发明公开了一种隧道电流放大晶体管，其涉及CMOS超大规模半导体集成电路（ULSI）中的场效应晶体管逻辑器件的面积。隧道电流放大晶体管包括半导体衬底，栅极电介质层，发射极，漏极，浮动隧道基极和控制栅极，其中漏极，浮动隧道基极和控制栅极形成传统的TFET结构，以及发射极的掺杂类型与浮动隧道基体的掺杂类型相反。发射极的位置相对于漏极在浮动基底的另一侧。发射极和浮动隧道基底之间的半导体类型与浮动隧道基底的相同。与常规TFET相比，本发明的隧道电流放大晶体管可以有效地增加器件的导通电流，并提高器件的驱动能力。

7. 发明授权

US08513639B2 Resistive-switching memory and fabrication method thereof 有权
标题翻译：电阻式开关存储器及其制造方法
公开(公告)号：US08513639B2
公开(公告)日：2013-08-20
申请号：US13254570
申请日：2011-04-12
申请人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
发明人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.
摘要翻译：本发明公开了一种电阻式开关存储器及其制造方法。电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部电极为板状。底部电极的峰值结构降低了器件的功耗。其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。整个制造工艺简单，可以实现高集成度的装置。

8. 发明申请

US20120181585A1 Combined-source Mos Transistor with Comb-shaped Gate, and Method for Manufacturing the Same 有权
标题翻译：具有梳状门的组合源Mos晶体管及其制造方法
公开(公告)号：US20120181585A1
公开(公告)日：2012-07-19
申请号：US13318333
申请日：2011-04-01
申请人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yangyuan Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/66643 , H01L29/7391 , H01L29/7839
摘要： The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same. The combined-source MOS transistor includes: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, wherein a Schottky source region is connected to a side of the highly-doped source region which is far from a channel, one end of the control gate extends to the highly-doped source region, the extended gate region is an extension gate in a form of a comb-shaped and the original control gate region is a main gate; an active region covered by the extension gate is also a channel region, and is a substrate material; the highly-doped source region which is formed by highly doping is located on both sides of each comb finger of the extension gate; and a Schottky junction is formed at a location where the Schottky source region and the channel under the extension gate are located. As compared with an existing MOSFET, in the invention, a higher turn-on current, a lower leakage current and a steeper subthreshold slope may be obtained under the same process condition and the same active region size.
摘要翻译：本发明公开了一种具有肖特基势垒和梳状栅极结构的组合源MOS晶体管及其制造方法。组合源MOS晶体管包括：控制栅极电极层，栅极电介质层，半导体衬底，高掺杂源极区域和高掺杂漏极区域，其中肖特基源极区域连接到高度远离通道的掺杂源极区域，控制栅极的一端延伸到高掺杂源极区域，延伸栅极区域是梳状形式的延伸栅极，并且原始控制栅极区域是大门; 由延伸栅极覆盖的有源区域也是沟道区域，并且是衬底材料; 通过高掺杂形成的高掺杂源区位于延伸门的每个梳齿的两侧; 并且在肖特基源区域和延伸门下方的沟道所在的位置处形成肖特基结。与现有的MOSFET相比，在本发明中，可以在相同的工艺条件和相同的有源区域尺寸下获得较高的导通电流，较低的漏电流和更陡的亚阈值斜率。

9. 发明授权

US09099500B2 Programmable array of silicon nanowire field effect transistor and method for fabricating the same 有权
标题翻译：硅纳米线场效应晶体管的可编程阵列及其制造方法
公开(公告)号：US09099500B2
公开(公告)日：2015-08-04
申请号：US13503240
申请日：2011-11-18
申请人： Ru Huang , Jibin Zou , Runsheng Wang , Jiewen Fan , Changze Liu , Yangyuan Wang
发明人： Ru Huang , Jibin Zou , Runsheng Wang , Jiewen Fan , Changze Liu , Yangyuan Wang
IPC分类号： H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/775 , B82Y10/00 , H01L21/02 , B82Y99/00
CPC分类号： H01L29/66977 , B82Y10/00 , B82Y99/00 , H01L21/02603 , H01L21/823828 , H01L21/823885 , H01L27/092 , H01L29/0673 , H01L29/66439 , H01L29/775
摘要： The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.
摘要翻译：本发明公开了一种基于硅纳米线场效应晶体管的六边形可编程阵列及其制造方法。阵列包括纳米线器件，纳米线器件连接区域和栅极连接区域，其中纳米线器件具有圆筒形状，并且包括硅纳米线通道，栅极介电层和栅极区域，纳米线通道被包围通过所述栅极介电层，并且所述栅极介电层被所述栅极区域包围; 纳米线器件以六边形形式布置以形成编程单元，纳米线器件连接区域是三个纳米线器件的连接节点并且固定到硅支撑体。本发明可以实现互连的复杂控制逻辑，并且适用于具有高集成度和高速度的数字/模拟和混合信号电路。

10. 发明授权

US09018968B2 Method for testing density and location of gate dielectric layer trap of semiconductor device 有权
标题翻译：半导体器件栅极介质层陷阱的密度和位置测试方法
公开(公告)号：US09018968B2
公开(公告)日：2015-04-28
申请号：US13879967
申请日：2012-02-28
申请人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
发明人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
IPC分类号： G01R31/02 , G01R31/26 , H01L21/66
CPC分类号： G01R31/2642 , G01R31/2621 , H01L22/14 , H01L22/34
摘要： Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.
摘要翻译：提出了一种用于测试半导体器件的栅介质层陷阱的密度和位置的方法。测试方法使用由泄漏路径产生的栅极泄漏电流来测试具有小面积（有效沟道面积小于0.5平方微米）的半导体器件的栅极介电层中的阱密度和二维陷阱位置。本发明特别适用于测试具有超小面积（有效通道面积小于0.05平方微米）的器件。在不同材料和不同工艺的情况下，本方法可以获得栅极电介质层的陷阱分布情况。在本方法中，器件要求简单，测试结构简单，测试成本低，测试快速，可在短时间内获得器件栅极电介质层的陷阱分布，适合用于大批量的自动测试，特别适用于超小型半导体器件制造过程中的过程监控和成品质量检测。

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