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1. 发明授权

US09142768B2 Resistive memory with small electrode and method for fabricating the same 有权
标题翻译：具有小电极的电阻记忆及其制造方法
公开(公告)号：US09142768B2
公开(公告)日：2015-09-22
申请号：US13698799
申请日：2012-05-02
申请人： Yimao Cai , Jun Mao , Ru Huang , Shenghu Tan , Yinglong Huang , Yue Pan
发明人： Yimao Cai , Jun Mao , Ru Huang , Shenghu Tan , Yinglong Huang , Yue Pan
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625
摘要： Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.
摘要翻译：公开了涉及具有与ULSI中的半导体电阻性存储器的领域相关的具有小电极的电阻性存储器的系统和方法。示例性电阻存储器可以依次包括Al电极层，SiO 2层，Si层，电阻材料层和下电极层，其中Al电极层和电阻材料层通过一个或多个导电沟道电连接并且通过SiO 2层中的缺陷将Al材料穿过Si层而将Si材料溶解到Al材料中而形成导电通道。方法可以包括在衬底上形成下电极层，电阻层，Si层和SiO 2层; 在SiO 2层上制造Al电极层; 对所得到的结构进行退火处理。与本文的创新一致，可以通过常规方法获得小电极。

2. 发明授权

US08942036B2 Method for achieving four-bit storage using flash memory having splitting trench gate 有权
标题翻译：用于使用具有分裂沟槽栅极的闪存实现四位存储的方法
公开(公告)号：US08942036B2
公开(公告)日：2015-01-27
申请号：US13499596
申请日：2011-10-14
申请人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
发明人： Yimao Cai , Ru Huang , Shiqiang Qin , Poren Tang , Yu Tang , Shenghu Tan , Xin Huang , Yue Pan
IPC分类号： G11C11/40 , H01L29/423 , G11C16/04 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42352 , G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.
摘要翻译：本发明公开了一种通过使用具有分割沟槽栅的闪存来实现四位存储的方法。具有分割沟槽栅的闪速存储器在中国专利No.200710105964.2中公开。在两个沟槽中的每一个与沟道接触的一侧，通过使用沟道热电子注入方法实现电子编程; 并且在另一侧，两个沟槽中的每一个与源极或漏极接触，通过使用FN注入方法来实现电子编程，使得通过改变器件的四位存储器的功能来实现一种编程模式。因此，提高了存储密度的装置的性能。

3. 发明授权

US08513639B2 Resistive-switching memory and fabrication method thereof 有权
标题翻译：电阻式开关存储器及其制造方法
公开(公告)号：US08513639B2
公开(公告)日：2013-08-20
申请号：US13254570
申请日：2011-04-12
申请人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
发明人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.
摘要翻译：本发明公开了一种电阻式开关存储器及其制造方法。电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部电极为板状。底部电极的峰值结构降低了器件的功耗。其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。整个制造工艺简单，可以实现高集成度的装置。

4. 发明授权

US08536639B2 I-shape floating gate for flash memory device and fabricating the same 有权
标题翻译：用于闪存器件的I形浮动栅极和制造它们
公开(公告)号：US08536639B2
公开(公告)日：2013-09-17
申请号：US13498585
申请日：2011-11-30
申请人： Yimao Cai , Song Mei , Ru Huang
发明人： Yimao Cai , Song Mei , Ru Huang
IPC分类号： H01L29/788 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273
摘要： The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.
摘要翻译：本发明公开了一种闪存器件的浮动栅极结构及其制造方法，涉及超大规模集成电路的制造技术中的非易失性存储器。在本发明中，通过在闪速存储器的标准处理中，即通过添加三个步骤的沉积，两个步骤的蚀刻和CMP的一个步骤来修改浮动栅极的制造，形成一个形状的浮动栅极。除了这些步骤之外，所有其他步骤与闪存过程的标准过程相同。通过本发明，可以有效地改善耦合比，并且可以降低相邻器件之间的串扰，而不增加额外的光掩模，并且几乎不增加工艺复杂性，这对于提高编程速度和可靠性非常重要。

5. 发明授权

US08526242B2 Flash memory and fabrication method and operation method for the same 有权
标题翻译：闪存及其制作方法及操作方法相同
公开(公告)号：US08526242B2
公开(公告)日：2013-09-03
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

6. 发明申请

US20120099381A1 EMBEDDED NON-VOLATILE MEMORY CELL, OPERATION METHOD AND MEMORY ARRAY THEREOF 审中-公开
标题翻译：嵌入式非易失性存储器单元，其操作方法和存储器阵列
公开(公告)号：US20120099381A1
公开(公告)日：2012-04-26
申请号：US13380414
申请日：2011-05-19
申请人： Yimao Cai , Poren Tang , Ru Huang , Xiaoyan Xu
发明人： Yimao Cai , Poren Tang , Ru Huang , Xiaoyan Xu
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： G11C16/0433 , H01L27/11526
摘要： The present invention discloses an embedded non-volatile memory cell, an operation method and a memory array thereof. The method includes using a gate of a selection transistor as a floating gate of a memory, and using a source electrode and a drain electrode of the selection transistor as a source electrode and a drain electrode of the memory; and then changing a threshold of the device by varying the electrode voltages, thereby realizing a storage and change of information. The invention has advantages of a small area, a low operating voltage, high operating speed and high reliability.
摘要翻译：本发明公开了一种嵌入式非易失性存储单元，其操作方法及其存储器阵列。该方法包括使用选择晶体管的栅极作为存储器的浮置栅极，并且使用选择晶体管的源电极和漏电极作为存储器的源电极和漏电极; 然后通过改变电极电压来改变器件的阈值，从而实现信息的存储和改变。本发明具有面积小，工作电压低，工作速度快，可靠性高等优点。

7. 发明授权

US08633465B2 Multilevel resistive memory having large storage capacity 有权
标题翻译：具有大存储容量的多电阻电阻存储器
公开(公告)号：US08633465B2
公开(公告)日：2014-01-21
申请号：US13513155
申请日：2012-02-08
申请人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
发明人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
摘要翻译：本发明公开了一种具有大存储容量的多电平电阻存储器，属于电阻式存储器的制造技术领域。电阻性存储器包括顶电极和底电极，以及插入在顶电极和底电极之间的多个开关层和有缺陷层的组合，其中，顶电极和底电极分别与开关层（诸如Ta 2 O 5，TiO 2，HfO 2的膜）和缺陷层（诸如Ti，Au，Ag的金属膜）介于切换层之间。通过使用本发明，可以提高电阻式存储器的存储容量。

8. 发明授权

US08593848B2 Programming method for programming flash memory array structure 有权
标题翻译： Flash存储阵列结构编程方法
公开(公告)号：US08593848B2
公开(公告)日：2013-11-26
申请号：US13146005
申请日：2011-04-21
申请人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
发明人： Yimao Cai , Ru Huang , Poren Tang , Shiqiang Qin
IPC分类号： G11C5/06
CPC分类号： G11C16/10 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.
摘要翻译：本发明提供一种闪存阵列结构及其编程方法，涉及超大规模集成电路制造技术中非易失性存储器的技术领域。本发明的闪速存储器阵列包括连接到存储单元的存储单元，字线和位线，其中连接到存储单元的控制栅极的字线和连接到存储单元的漏极端子的位线不垂直相互交叉但彼此成角度; 沿两个位线之间的通道方向彼此相邻的两个存储单元的控制栅极分别由两个字线控制，其漏极端分别由两个位线控制，并且其源极端子被共享。本发明还提供了一种用于编程闪存阵列结构的方法，其可以实现具有低功耗的编程。

9. 发明申请

US20130069031A1 MULTILEVEL RESISTIVE MEMORY HAVING LARGE STORAGE CAPACITY 有权
标题翻译：具有大容量存储容量的多电阻存储器
公开(公告)号：US20130069031A1
公开(公告)日：2013-03-21
申请号：US13513155
申请日：2012-02-08
申请人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
发明人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
摘要翻译：本发明公开了一种具有大存储容量的多电平电阻存储器，属于电阻式存储器的制造技术领域。电阻性存储器包括顶电极和底电极，以及插入在顶电极和底电极之间的多个开关层和有缺陷层的组合，其中，顶电极和底电极分别与开关层（诸如Ta 2 O 5，TiO 2，HfO 2的膜）和缺陷层（诸如Ti，Au，Ag的金属膜）介于切换层之间。通过使用本发明，可以提高电阻式存储器的存储容量。

10. 发明申请

US20120241712A1 Resistive-Switching Memory and Fabrication Method Thereof 有权
标题翻译：电阻式开关存储器及其制作方法
公开(公告)号：US20120241712A1
公开(公告)日：2012-09-27
申请号：US13254570
申请日：2011-04-12
申请人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
发明人： Yimao Cai , Ru Huang , Yangyuan Wang , Yinglong Huang
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： H01L45/1233 , H01L27/2472 , H01L45/08 , H01L45/085 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.
摘要翻译：本发明公开了一种电阻式开关存储器及其制造方法。电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部电极为板状。底部电极的峰值结构降低了器件的功耗。其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。整个制造工艺简单，可以实现高集成度的装置。

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