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1. 发明申请

US20080303098A1 Semiconductor Device Manufactured Using a Method to Reduce CMP Damage to Low-K Dielectric Material 审中-公开
标题翻译：使用减少对低K电介质材料的CMP损伤的方法制造的半导体器件
公开(公告)号：US20080303098A1
公开(公告)日：2008-12-11
申请号：US11759288
申请日：2007-06-07
申请人： Yaojian Leng , Robert D. Slater , Nathan J. Kruse
发明人： Yaojian Leng , Robert D. Slater , Nathan J. Kruse
IPC分类号： H01L29/76 , H01L21/302
CPC分类号： H01L21/7684 , H01L21/76829 , H01L21/76865
摘要： In one aspect, there is provided a method of manufacturing a semiconductor device. The method comprises depositing a barrier layer over a low-k dielectric layer located over a semiconductor substrate over which a metal layer is deposited. A chemical mechanical polish process is used to remove a portion of the metal layer and the barrier layer and a dry etch is used to remove a remaining portion of the barrier layer.
摘要翻译：一方面，提供一种制造半导体器件的方法。该方法包括在位于半导体衬底上的低k电介质层上沉积阻挡层，在其上沉积金属层。使用化学机械抛光工艺来去除金属层和阻挡层的一部分，并且使用干蚀刻去除阻挡层的剩余部分。

2. 发明授权

US07344987B2 Method for CMP with variable down-force adjustment 有权
标题翻译：具有可变下压力调整的CMP方法
公开(公告)号：US07344987B2
公开(公告)日：2008-03-18
申请号：US11445669
申请日：2006-06-02
申请人： Yaojian Leng , Nilesh Shantaram Doke , Stanley Monroe Smith
发明人： Yaojian Leng , Nilesh Shantaram Doke , Stanley Monroe Smith
IPC分类号： H01L21/302
CPC分类号： H01L21/3212 , B24B37/013 , B24B37/042 , B24B49/16 , H01L22/26
摘要： The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed. At least one of the down-force steps is modified, based on if one of the down-force steps exceeds an acceptable tolerance associated therewith. Other systems and methods are also disclosed.
摘要翻译：本发明涉及一种进行化学机械抛光的方法。执行高下推力步骤。执行低下推力步骤。基于下降力步骤之一超过与其相关联的可接受公差，至少一个下压步骤被修改。还公开了其它系统和方法。

3. 发明授权

US06965136B2 Photon-blocking layer 有权
公开(公告)号：US06965136B2
公开(公告)日：2005-11-15
申请号：US10684617
申请日：2003-10-14
申请人： Yaojian Leng , Honglin Guo , Joe W. McPherson
发明人： Yaojian Leng , Honglin Guo , Joe W. McPherson
IPC分类号： H01L21/768 , H01L23/552 , H01L31/0232
CPC分类号： H01L23/552 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).

4. 发明授权

US06806193B2 CMP in-situ conditioning with pad and retaining ring clean 有权
标题翻译： CMP原位调理用垫和保持环清洁
公开(公告)号：US06806193B2
公开(公告)日：2004-10-19
申请号：US10342547
申请日：2003-01-15
申请人： Vincent C. Korthuis , Mona Eissa , Yaojian Leng , Syed Hamid
发明人： Vincent C. Korthuis , Mona Eissa , Yaojian Leng , Syed Hamid
IPC分类号： H01L21304
CPC分类号： B24B37/32 , B24B53/017 , C11D3/0073 , C11D3/2086 , C11D7/265 , C11D11/0047
摘要： A method for preconditioning a CMP polishing pad and retaining ring prior to semiconductor wafer polishing. In the method of the present invention, the retaining ring is lowered to contact the rotating polishing pad, and a cleaning chemistry of ammonium citrate is applied to the pad. In an alternative embodiment, the cleaning chemistry comprises an aqueous solution of ammonium citrate, and a surfactant and/or copper inhibitor. After a sustained preconditioning period in which the retaining ring and polishing pad are polished, the pad is rinsed, lowering particulate buildup on the pad between wafer polishing steps, and bringing defect levels into an equilibrium state prior to each wafer polishing step.
摘要翻译：一种用于在半导体晶片抛光之前预处理CMP抛光垫和保持环的方法。在本发明的方法中，保持环降低以接触旋转的抛光垫，并且将枸橼酸铵的清洁化学品施加到垫上。在替代实施方案中，清洁化学品包括柠檬酸铵水溶液和表面活性剂和/或铜抑制剂。在保持环和抛光垫被抛光的持续预处理阶段之后，漂洗垫，在晶片抛光步骤之间降低垫上的颗粒积聚，并在每个晶片抛光步骤之前使缺陷水平达到平衡状态。

5. 发明授权

US06553332B2 Method for evaluating process chambers used for semiconductor manufacturing 有权
公开(公告)号：US06553332B2
公开(公告)日：2003-04-22
申请号：US09727186
申请日：2000-11-30
申请人： Yaojian Leng
发明人： Yaojian Leng
IPC分类号： G06F1500
CPC分类号： H01L22/20 , H01L22/34 , Y10S438/924 , Y10S438/935
摘要： A process chamber (12) is used for plasma etching of a wafer (21) disposed therein. A gas mixture supplied to the chamber eventually passes through openings (28) in a baffle plate (27). After the chamber has been cleaned, several test wafers are etched under conditions which are equivalent, except that a different gas pressure is used for each wafer. The effective etch rates are measured from these wafers, and used to extrapolate a reference curve (141) representing effective etch rate relative to pressure. During subsequent production use of the chamber, a similar procedure is periodically used to generate a test curve (142). The peak values (143, 144) of the reference and test curves are compared (147) to monitor process drift within the chamber. The peak values of respective curves obtained from two or more similar chambers can be compared to evaluate performance differences between the chambers.

6. 发明授权

US09716167B2 Trench DMOS transistor with reduced gate-to-drain capacitance 有权
公开(公告)号：US09716167B2
公开(公告)日：2017-07-25
申请号：US13032405
申请日：2011-02-22
申请人： Yaojian Leng , Richard Wendell Foote, Jr. , Steven J. Adler
发明人： Yaojian Leng , Richard Wendell Foote, Jr. , Steven J. Adler
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/423
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/42368 , H01L29/66734 , H01L29/7809
摘要： A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.

7. 发明申请

US20120211826A1 Trench DMOS Transistor with Reduced Gate-to-Drain Capacitance 有权
标题翻译：具有降低栅极到漏极电容的沟槽DMOS晶体管
公开(公告)号：US20120211826A1
公开(公告)日：2012-08-23
申请号：US13032405
申请日：2011-02-22
申请人： Yaojian Leng , Richard Wendell Foote, JR. , Steven J. Adler
发明人： Yaojian Leng , Richard Wendell Foote, JR. , Steven J. Adler
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/42368 , H01L29/66734 , H01L29/7809
摘要： A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.
摘要翻译：具有非常低的导通状态漏极至源极电阻和高栅极至漏极电荷的沟槽DMOS晶体管包括位于栅极和漏极之间的一个或多个浮置岛，以减少栅极和漏极之间的电荷耦合，并有效降低栅 - 漏电容。

8. 发明授权

US08002611B2 Chemical mechanical polishing pad having improved groove pattern 有权
标题翻译：具有改进凹槽图案的化学机械抛光垫
公开(公告)号：US08002611B2
公开(公告)日：2011-08-23
申请号：US11964141
申请日：2007-12-26
申请人： Yanghua He , Jingqiu Chen , Yaojian Leng
发明人： Yanghua He , Jingqiu Chen , Yaojian Leng
IPC分类号： B24D11/00
CPC分类号： B24B37/26
摘要： A chemical mechanical polishing pad and method for chemical-mechanical polishing is provided, wherein the polishing pad has a plurality of first mesas and one or more second mesas defined on a surface thereof. The plurality of first mesas are generally distributed about the surface of the polishing pad, wherein each of the plurality of first mesas has a first surface area associated therewith. The one or more second mesas are associated with a center region of the polishing pad, wherein each of the one or more second mesas has a second surface area associated therewith. The second surface area is at least twice the first surface area.
摘要翻译：提供了一种用于化学机械抛光的化学机械抛光垫和方法，其中抛光垫具有多个第一台面和在其表面上限定的一个或多个第二台面。多个第一台面通常围绕抛光垫的表面分布，其中多个第一台面中的每一个具有与其相关联的第一表面区域。所述一个或多个第二台面与所述抛光垫的中心区域相关联，其中所述一个或多个第二台面中的每一个具有与其相关联的第二表面区域。第二表面积至少是第一表面积的两倍。

9. 发明申请

US20070281482A1 Method for CMP with variable down-force adjustment 有权
标题翻译：具有可变下压力调整的CMP方法
公开(公告)号：US20070281482A1
公开(公告)日：2007-12-06
申请号：US11445669
申请日：2006-06-02
申请人： Yaojian Leng , Nilesh Doke , Stanley Smith
发明人： Yaojian Leng , Nilesh Doke , Stanley Smith
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3212 , B24B37/013 , B24B37/042 , B24B49/16 , H01L22/26
摘要： The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed. At least one of the down-force steps is modified, based on if one of the down-force steps exceeds an acceptable tolerance associated therewith. Other systems and methods are also disclosed.
摘要翻译：本发明涉及一种进行化学机械抛光的方法。执行高下推力步骤。执行低下推力步骤。基于下降力步骤之一超过与其相关联的可接受公差，至少一个下压步骤被修改。还公开了其它系统和方法。

10. 发明授权

US06908851B2 Corrosion resistance for copper interconnects 有权
标题翻译：铜互连的耐腐蚀性
公开(公告)号：US06908851B2
公开(公告)日：2005-06-21
申请号：US10463948
申请日：2003-06-17
申请人： Yaojian Leng , Linlin Chen
发明人： Yaojian Leng , Linlin Chen
IPC分类号： H01L21/288 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/288 , H01L21/76849
摘要： A method to reduce the copper corrosion of copper interconnects by forming 70 at least one conductive displacement plating layer on the copper interconnects. Also, a method to eliminate the copper corrosion of copper interconnects by forming 70 at least one conductive displacement plating layer on the copper interconnects.
摘要翻译：一种通过在铜互连上形成70个至少一个导电位移镀层来减少铜互连铜腐蚀的方法。另外，通过在铜互连上形成70个至少一个导电位移镀层来消除铜互连铜腐蚀的方法。

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