专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140003485A1 ON-THE-FLY COMPENSATION OF SAMPLING FREQUENCY AND PHASE OFFSET IN RECEIVER PERFORMING ULTRA-HIGH-SPEED WIRELESS COMMUNICATION 有权
标题翻译：接收机执行超高速无线通信的采样频率和相位偏移的实时补偿
公开(公告)号：US20140003485A1
公开(公告)日：2014-01-02
申请号：US14004333
申请日：2012-03-02
申请人： Yasunao Katayama , Yasuteru Kohda , Daiju Nakano
发明人： Yasunao Katayama , Yasuteru Kohda , Daiju Nakano
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L7/0029 , H04L7/10 , H04L25/03038 , H04L27/22 , H04L27/38 , H04L2025/03471 , H04L2025/03605 , H04L2025/03687
摘要： Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner. In this configuration, a resampling filter circuit, an equalization filter circuit and a decimation filter circuit are realized in a single compensation filter circuit, which is much smaller than the prior art circuits in terms of size.
摘要翻译：接收到的二次采样数据由接收机多相接收，使用自适应算法应用反馈，并且当数据移位时，补偿滤波器的滤波器系数（抽头系数序列）同时移位。可以使用组合使用初始值是从接收信号的前同步码和报头获得的相关值的抽头滤波器和波前对准器来对采样频率和相位偏移进行补偿。在该配置中，在单个补偿滤波器电路中实现了重采样滤波器电路，均衡滤波器电路和抽取滤波器电路，其在尺寸方面比现有技术的电路小得多。

2. 发明授权

US08346080B2 Optical network system and memory access method 失效
标题翻译：光网络系统和内存访问方式
公开(公告)号：US08346080B2
公开(公告)日：2013-01-01
申请号：US12764206
申请日：2010-04-21
申请人： Yasunao Katayama , Atsuya Okazaki
发明人： Yasunao Katayama , Atsuya Okazaki
IPC分类号： H04B10/00
CPC分类号： H04J14/0286 , H04J14/0254 , H04J14/0257 , H04J14/0267 , H04J14/08 , H04Q11/0062 , H04Q11/0066 , H04Q2011/0092
摘要： A system and method for handling accesses by nodes connected to a ring network, using time division multiplexing (TDM). The system includes: nodes capable of receiving only an optical signal of a wavelength or positional space allocated to the node, and of transmitting optical signals of wavelengths allocated to other nodes; and a ring network that performs TDM transmission of optical signals. The ring network has slots for transmitting optical signals of individual wavelengths. Information indicates whether an optical signal to be transmitted exists in each of the slots. Nodes include means for updating the information indicating that the optical signal exists and determining means for updating the information and determining, on the basis of the information, whether to transmit the optical signal.
摘要翻译：一种用于通过使用时分复用（TDM）来处理连接到环形网络的节点的接入的系统和方法。该系统包括：能够仅接收分配给该节点的波长或位置空间的光信号并发送分配给其他节点的波长的光信号的节点; 以及执行光信号的TDM传输的环网。环形网络具有用于发射各个波长的光信号的槽。信息表示每个时隙中是否存在要发送的光信号。节点包括用于更新指示光信号存在的信息的装置和用于更新信息的确定装置，并且基于该信息确定是否发送光信号。

3. 发明申请

US20120143936A1 RADIX-8 FIXED-POINT FFT LOGIC CIRCUIT CHARACTERIZED BY PRESERVATION OF SQUARE ROOT-i OPERATION 有权
标题翻译： RADIX-8定点FFT逻辑电路，通过保存方圆操作表征
公开(公告)号：US20120143936A1
公开(公告)日：2012-06-07
申请号：US13300710
申请日：2011-11-21
申请人： Yasunao Katayama , Kohji Takano
发明人： Yasunao Katayama , Kohji Takano
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , G06F17/141
摘要： A system and method to reduce roundoff error of Fast Fourier transform (FFT) operation. Data which comes out as an irrational number (a square root) out of twiddle factors on a complex plane, included in a butterfly operation (8p) is preserved intentionally without being calculated in one stage of multiple stages of a multi-stage pipelined FFT, and when it occurs again in a later stage, an operation to multiply the two twiddle factors with each other is performed. This enables to eliminate roundoff errors during the butterfly operation 8p of radix-8. Other applications are also possible such as by overlaying a further stage by a butterfly operation of radix-2 or radix-4.
摘要翻译：一种降低快速傅里叶变换（FFT）运算误差的方法。包含在蝴蝶操作（8p）中的复平面上的旋转因子中出现的非理性数（数平方根）的数据被有意保留，而不是在多级流水线FFT的多级的一个阶段中计算出来，并且当在稍后阶段再次发生时，执行将两个旋转因子彼此相乘的操作。这使得能够在基数-8的蝶形运算8p期间消除舍入误差。其他应用也是可能的，例如通过用基数-2或基数-4的蝶形运算覆盖另外的阶段。

4. 发明授权

US08005161B2 Method, hardware product, and computer program product for performing high data rate wireless transmission 失效
标题翻译：用于执行高数据速率无线传输的方法，硬件产品和计算机程序产品
公开(公告)号：US08005161B2
公开(公告)日：2011-08-23
申请号：US12113251
申请日：2008-05-01
申请人： Yasunao Katayama , Daiju Nakano
发明人： Yasunao Katayama , Daiju Nakano
IPC分类号： H04L27/12 , H04L27/14
CPC分类号： H04L27/122 , H04L27/14 , H04L27/144
摘要： A method, a hardware product, and a computer program product for performing high data rate wireless transmission and reception. Minimum shift-keyed (MSK) data is transmitted by multiplexing a first MSK data stream and a second MSK data stream wherein the first MSK data stream is substantially 90-degree phase-shifted with respect to the second MSK data stream. The transmitted MSK data is received by performing phase recovery and demodulation using an FM discriminator having a demodulation circuit for implementing a 45-degree phase shift prior to demodulation.
摘要翻译：一种用于执行高数据速率无线传输和接收的方法，硬件产品和计算机程序产品。通过复用第一MSK数据流和第二MSK数据流来发送最小移位键控（MSK）数据，其中第一MSK数据流相对于第二MSK数据流基本上是90度相移。通过使用具有用于在解调之前实现45度相移的解调电路的FM鉴频器执行相位恢复和解调来接收所发送的MSK数据。

5. 发明申请

US20110075776A1 Method and circuit for digitally filtering a signal 有权
标题翻译：用于数字滤波信号的方法和电路
公开(公告)号：US20110075776A1
公开(公告)日：2011-03-31
申请号：US12924535
申请日：2010-09-29
申请人： Yasunao Katayama , Daiju Nakano , Kohji Takano
发明人： Yasunao Katayama , Daiju Nakano , Kohji Takano
IPC分类号： H04B1/10
CPC分类号： H04L27/34 , H04L25/0232
摘要： A method and circuit that gives a sequence pattern that represents directions of positive and negative transitions of the phase that continue over a predetermined number from a certain reference symbol to an adjoining next reference symbol; finds (heuristically) one or more interpolate symbols that meet conditions (such as standards for power spectra) of a predetermined frequency spectrum, i.e., band, and a predetermined (range of) amplitude with reference to the given sequence pattern; and stores the found sequence pattern and a phase value and an amplitude value corresponding to the found one or more interpolate symbols in a memory as a lookup table against the prepared memory area.
摘要翻译：一种方法和电路，其给出表示从某个参考符号到相邻的下一个参考符号在预定数目上继续的相位的正和负转变的方向的序列模式; 参考给定的序列模式，发现（启发式）一个或多个满足预定频谱（即，频带）和预定（幅度范围）的条件（诸如功率谱的标准）的内插符号; 并将所找到的序列模式和与所找到的一个或多个内插符号相对应的相位值和振幅值存储在存储器中作为针对准备好的存储器区域的查找表。

6. 发明申请

US20080022182A1 ENCODING AND DECODING METHOD FOR PACKET RECOVERY 失效
标题翻译：用于分组恢复的编码和解码方法
公开(公告)号：US20080022182A1
公开(公告)日：2008-01-24
申请号：US11773117
申请日：2007-07-03
申请人： Yasunao Katayama , Daiju Nakano
发明人： Yasunao Katayama , Daiju Nakano
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/1515 , H03M13/29 , H03M13/373
摘要： The present invention discloses a Partially-Overlapped Block (POB) code used in a new encoding method. In this encoding method, a POB code is implemented by combining a plurality of different block codes so that the block codes partially overlap one another. A decoding method corresponding to this encoding method is also disclosed. In addition, disclosed is a method for recovering a plurality of packets by using a loss correction capability of this code. The present invention makes it possible to recover the larger number of packets than the number of added redundant packets per frame, by reusing redundant information of neighboring frames effectively, without increasing the asymptotic complexity of its decoding algorithm.
摘要翻译：本发明公开了一种在新的编码方法中使用的部分重叠块（POB）。在该编码方法中，通过组合多个不同的块码来实现POB码，使得块码部分重叠。还公开了与该编码方法对应的解码方法。此外，公开了通过使用该代码的损失校正能力来恢复多个分组的方法。本发明可以通过重复使用相邻帧的冗余信息而不增加其解码算法的渐近复杂度来恢复比每帧增加的冗余分组数更多的数据包。

7. 发明授权

US07010738B2 Combinational circuit, and encoder, decoder and semiconductor device using this combinational circuit 失效
标题翻译：组合电路，以及使用该组合电路的编码器，解码器和半导体器件
公开(公告)号：US07010738B2
公开(公告)日：2006-03-07
申请号：US10091774
申请日：2002-03-06
申请人： Sumio Morioka , Yasunao Katayama , Toshiyuki Yamane
发明人： Sumio Morioka , Yasunao Katayama , Toshiyuki Yamane
IPC分类号： H03M13/00
CPC分类号： H03M13/6502 , H03M13/1515 , H03M13/1525 , H03M13/1555 , H03M13/158 , H03M13/37
摘要： A combinational circuit comprises: a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2m) (m is an integer equal to or greater than 2), wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. Further, according to the present invention, these multipliers each include an adder connected between an AND calculator and an output side XOR calculator, wherein the output side XOR calculator is used in common, and wherein the outputs of the AND calculators in the multipliers are added by the adders, and the addition results are calculated by the output side XOR calculator that is used in common.
摘要翻译：一种组合电路包括：多个乘法器，在伽罗瓦扩展字段GF（2≤M）中独立地执行编码数字信号的两个或多个乘法运算（m是等于或大于2的整数），其中所述乘法器包括输入侧XOR计算器，AND计算器和输出侧XOR计算器，并且其中所述乘法器共享输入侧XOR计算器。此外，根据本发明，这些乘法器各自包括连接在AND计算器和输出侧XOR计算器之间的加法器，其中输出侧XOR计算器被共同使用，并且其中乘法器中的AND计算器的输出被加上并且加法结果由共同使用的输出侧XOR计算器计算。

8. 发明授权

US06928601B2 Decoding circuit, and decoder, decoding method and semiconductor device that use the decoding circuit 失效
标题翻译：解码电路，解码器，解码方法和使用解码电路的半导体器件
公开(公告)号：US06928601B2
公开(公告)日：2005-08-09
申请号：US10091840
申请日：2002-03-06
申请人： Yasunao Katayama , Sumio Morioka , Toshiyuki Yamane
发明人： Yasunao Katayama , Sumio Morioka , Toshiyuki Yamane
IPC分类号： G06F11/10 , H03M13/15 , H03M13/27 , H04L1/00 , H03M13/00 , G06F7/00
CPC分类号： H03M13/1555 , H03M13/1525
摘要： A decoding circuit used to correct an error in a digital signal includes: an input unit for entering coded digital signals ID in parallel in accordance with the number of interleaved codes; a processor including an error locator polynomial calculator and an error value polynomial calculator for processing data obtained serially from the interleaved codes that are received by the input unit; and an output unit for correcting errors by employing the output data that are received from the processor and the digital signals ID, and for outputting in parallel the obtained digital signals OD, for which an error has been corrected by a linear calculation on a Galois field, in accordance with the number of interleaved codes.
摘要翻译：用于校正数字信号中的误差的解码电路包括：输入单元，用于根据交错码并行输入编码数字信号ID; 处理器，包括误差定位多项式计算器和误差值多项式计算器，用于处理由输入单元接收的交织代码串行获得的数据; 以及输出单元，用于通过采用从处理器接收的输出数据和数字信号ID来校正误差，并且通过在伽罗瓦域上的线性计算并行地输出所获得的已经校正了误差的数字信号OD ，根据交错码的数量。

9. 发明授权

US06487691B1 Reed-solomon decoder 失效
标题翻译：里德独奏解码器
公开(公告)号：US06487691B1
公开(公告)日：2002-11-26
申请号：US09401051
申请日：1999-09-22
申请人： Yasunao Katayama , Sumio Morioka
发明人： Yasunao Katayama , Sumio Morioka
IPC分类号： H03M1300
CPC分类号： H03M13/6561 , H03M13/1515 , H03M13/1555
摘要： A Reed-Solomon decoder that can correct t errors or fewer which includes: a syndrome calculation circuit for calculating syndromes Sj (J=0, 1, . . . , 2t−1) using the first codeword Yi (i=0, 1, . . . , n−1) (so-called received codeword) that may include errors; and a coefficient calculation circuit for, by using the syndromes Sj, calculating coefficients &Lgr;k (k=1, . . . , e) of an error-locator polynomial. The coefficients &Lgr;k correspond in number to e estimated errors (e≦t
摘要翻译：可以校正t误差或更少的Reed-Solomon解码器，其包括：使用第一码字Yi（i = 0,1，...）来计算综合征Sj（J = 0,1，...，2t-1）的校正子计算电路， ...，n-1）（所谓的接收码字），可能包括错误; 以及用于通过使用校正子Sj的误差定位多项式的计算系数LAMBDk（k = 1，...，e）的系数计算电路。系数LAMBDk在数量上对应于估计的误差（e <= t

10. 发明授权

US5875452A DRAM/SRAM with uniform access time using buffers, write back, address decode, read/write and refresh controllers 失效
标题翻译：使用缓冲区，写回，地址解码，读/写和刷新控制器的DRAM / SRAM具有统一的访问时间
公开(公告)号：US5875452A
公开(公告)日：1999-02-23
申请号：US764809
申请日：1996-12-12
申请人： Yasunao Katayama , Akashi Sato
发明人： Yasunao Katayama , Akashi Sato
IPC分类号： G11C11/401 , G11C7/10 , G11C11/406 , G06F12/00
CPC分类号： G11C11/406 , G11C7/1018 , G11C7/1039
摘要： A DRAM is provided that can carry out data reads or writes in a constant and short access time regardless of the timing with which the reads or writes, or refreshing are executed. When requests for reads from or writes to burst data are continuously input, row decoding (RD) and column decoding (CD) by a row decoder 42 and a column decoder 52, an array access (AR) and precharging (PR) by a data line driver 24, a bit switch 26, and a sense amplifier 28, and data transfer (TR) by a write buffer 52 and a read buffer 54 are executed in parallel in a pipelined manner. When the time has come to refresh a DRAM array 22, a refresh address held in a refresh controller 40 is output while the burst data is being transferred, and a series of refreshing operations comprising (RD), (AR), and (PR) is performed.
摘要翻译：提供了DRAM，其可以在恒定和短的访问时间内执行数据读取或写入，而与执行读取或写入或刷新的时间无关。当连续地输入对脉冲数据的读取或写入的请求时，由行解码器42和列解码器52进行行解码（RD）和列解码（CD），数据访问（AR）和预充电（PR）线路驱动器24，位开关26和读出放大器28以及由写入缓冲器52和读取缓冲器54进行的数据传输（TR）以流水线方式并行执行。当刷新DRAM阵列22的时刻到来时，输出在刷新控制器40中保存的刷新地址，同时在传输突发数据的同时，还包括（RD），（AR）和（PR）被执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式