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1. 发明授权

US08634884B2 Sliding-type portable terminal 有权
标题翻译：滑动型便携式终端
公开(公告)号：US08634884B2
公开(公告)日：2014-01-21
申请号：US12044476
申请日：2008-03-07
申请人： Yong-Kyu Kim , Jae-Gab Lee
发明人： Yong-Kyu Kim , Jae-Gab Lee
IPC分类号： H04M1/00 , H04M9/00
CPC分类号： H04M1/0239
摘要： A sliding-type portable terminal is provided. The portable terminal includes a first housing, a first guide member fixed to the first housing, a slide member coupled to the first guide member while facing the first guide member, the slide member being adapted to slide in a first direction under guidance of the first guide member, a second guide member fixed to the slide member, a second housing having a guide recess extending in a second direction so as to receive the second guide member, the second housing being coupled to the second guide member so as to slide in the second direction under guidance of the second guide member and an elastic member having a first end supported on the first guide member and a second end supported on the second housing so as to provide elastic force in such a direction that the first and second ends move away from each other. The sliding-type portable terminal is adapted for convenient use of not only mobile communication services, but also multimedia services.
摘要翻译：提供了一种滑动型便携式终端。便携式终端包括第一壳体，固定到第一壳体的第一引导构件，与第一引导构件相对的第一导向构件的滑动构件，滑动构件适于在第一方向上沿第一方向滑动，引导构件，固定到所述滑动构件的第二引导构件，具有沿第二方向延伸以便接收所述第二引导构件的引导凹部的第二壳体，所述第二壳体联接到所述第二引导构件以在所述第二引导构件中滑动在第二引导构件的引导下的第二方向和弹性构件，其具有支撑在第一引导构件上的第一端和支撑在第二壳体上的第二端，以便在第一和第二端移开的方向上提供弹力从彼此。滑动型便携式终端不仅适用于移动通信服务，还适用于多媒体业务。

2. 发明授权

US07964473B2 Method of filling an opening in the manufacturing of a semiconductor device 有权
标题翻译：在制造半导体器件时填充开口的方法
公开(公告)号：US07964473B2
公开(公告)日：2011-06-21
申请号：US12212676
申请日：2008-09-18
申请人： Yong-kyu Kim , Jin-ho Jeon , Kyoung-soo Kwon
发明人： Yong-kyu Kim , Jin-ho Jeon , Kyoung-soo Kwon
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A reliable gap-filling process is performed in the manufacturing of a semiconductor device. An apparatus for performing the gap-filling process includes a chamber in which a wafer chuck is disposed, a plasma generator for generating plasma used to etch the wafer, an end-point detection unit for detecting the point at which the etching of the wafer is to be terminated, and a controller connected to the end-point detection unit. The end-point detection unit monitors the structure being etched at a region outside the opening that is to be filled, and generates in real time data representative of the layer that is being etched. As soon as an underlying layer is exposed and begins to be etched, an end-point detection signal is generated and the etching process is terminated. In the case in which the layer being etched is an oxide layer, a uniform etching is achieved despite any irregularity that exists in the thickness to which the oxide layer is formed.
摘要翻译：在半导体器件的制造中执行可靠的间隙填充处理。用于执行间隙填充处理的装置包括其中设置有晶片卡盘的腔室，用于产生用于蚀刻晶片的等离子体的等离子体发生器，用于检测晶片蚀刻点的终点检测单元以及连接到端点检测单元的控制器。端点检测单元监视在要被填充的开口外的区域被蚀刻的结构，并且实时地产生代表被蚀刻的层的数据。一旦暴露底层并开始蚀刻，就产生端点检测信号，并终止蚀刻工艺。在蚀刻层是氧化物层的情况下，尽管在形成氧化物层的厚度中存在任何不规则性，但是实现了均匀的蚀刻。

3. 发明授权

US07580267B2 Portable terminal having sliding module 有权
标题翻译：便携式终端具有滑动模块
公开(公告)号：US07580267B2
公开(公告)日：2009-08-25
申请号：US11375059
申请日：2006-03-15
申请人： Yong-Kyu Kim
发明人： Yong-Kyu Kim
IPC分类号： H05K5/00
CPC分类号： H04M1/0237
摘要： A portable terminal includes a first housing, a second housing, and a sliding module. The second housing is slidably connected to the first housing such that the second housing slides longitudinally on the first housing to open or close a face of the first housing. The sliding module is interposed between the first housing and the second housing to slidably combine the second housing to the first housing. The sliding module includes a pair of guide rods and a guide plate. The guide rods are mounted spaced apart on the rear face of the second housing along a sliding direction of the second housing. The guide plate is fixed to a face of the first housing. The guide plate is slidably connected to the guide rods.
摘要翻译：便携式终端包括第一壳体，第二壳体和滑动模块。第二壳体可滑动地连接到第一壳体，使得第二壳体在第一壳体上纵向滑动以打开或关闭第一壳体的表面。滑动模块插入在第一壳体和第二壳体之间以将第二壳体可滑动地组合到第一壳体。滑动模块包括一对导向杆和导向板。引导杆沿着第二壳体的滑动方向间隔地安装在第二壳体的后表面上。引导板固定在第一壳体的表面上。引导板可滑动地连接到导杆。

4. 发明申请

US20060097773A1 Negative voltage generator circuit 失效
标题翻译：负电压发生器电路
公开(公告)号：US20060097773A1
公开(公告)日：2006-05-11
申请号：US11193814
申请日：2005-07-27
申请人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
发明人： Sang-Hee Kang , Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/071
摘要： The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.
摘要翻译：本发明涉及一种用于将半导体集成电路（IC）可靠地提供负电压的负电压产生电路。电荷泵送装置通过将电荷泵送到提供给第一节点和第二节点之一的预定水平来产生负电压。控制装置响应于负电压的电平，以预定间隔交替地提供按时钟交替的第一和第二泵送时钟信号。泵送控制器响应于第一和第二泵送时钟信号控制提供给第一节点和第二节点的电荷量。此外，复位控制器将电荷泵送装置的第一节点和第二节点复位为当第一和第二抽运时钟信号失活时的负电压的电平。

5. 发明申请

US20090184783A1 RESONANT STRUCTURE COMPRISING WIRE, RESONANT TUNNELING TRANSISTOR, AND METHOD FOR FABRICATING THE RESONANT STRUCTURE 有权
标题翻译：包含线，谐振隧道晶体管的谐振结构和用于制造谐振结构的方法
公开(公告)号：US20090184783A1
公开(公告)日：2009-07-23
申请号：US12357681
申请日：2009-01-22
申请人： Yun-kwon Park , Sung-Woo Hwang , Jea-Shik Shin , Byeoung-Ju Ha , Jae-Sung Rieh , In-Sang Song , Yong-Kyu Kim , Byeong-Kwon Ju , Hee-Tae Kim
发明人： Yun-kwon Park , Sung-Woo Hwang , Jea-Shik Shin , Byeoung-Ju Ha , Jae-Sung Rieh , In-Sang Song , Yong-Kyu Kim , Byeong-Kwon Ju , Hee-Tae Kim
IPC分类号： H01P7/00 , H01L21/30
CPC分类号： H01L29/0665 , B81B2201/0271 , B81C1/00142 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/49 , H01L29/78 , Y10S977/936 , Y10S977/937 , Y10S977/938
摘要： A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.
摘要翻译：提供了一种谐振结构，包括第一端子，面向第一端子的第二端子，连接第一端子和第二端子的导线单元，与导线单元隔开一定距离的第三端子，以及使导线单元谐振，以及形成在导线单元上并提供负电阻分量的势垒单元。因此，可以提高转导效率。

6. 发明授权

US07184331B2 Redundancy fuse control circuit and semiconductor memory device having the same and redundancy process method 有权
标题翻译：冗余保险丝控制电路和具有相同冗余处理方法的半导体存储器件
公开(公告)号：US07184331B2
公开(公告)日：2007-02-27
申请号：US11169947
申请日：2005-06-30
申请人： Yong-Kyu Kim , Sang-Hee Kang
发明人： Yong-Kyu Kim , Sang-Hee Kang
IPC分类号： G11C7/00
CPC分类号： G11C29/84 , G11C29/785
摘要： A semiconductor memory device including a fuse control circuit for providing with a plurality of fail word line addresses written in its own circuit in advance and outputting a redundancy signal representing that an input address is the same as one of the fail word line addresses, and a normal word line interruption signal, a redundancy word line controller for inputting the redundancy signal and activating a designated redundancy word line; and a normal word line controller, for activating a word line corresponding to the input word line address, which is operated or interrupted in response to the normal word line interruption signal, wherein the normal word line interruption signal has a first logic state (logic low) at a pre-charge interval or when a same address as one of the fail word line addresses is inputted, and has a second logic state (logic high) when a normal address is inputted, and the redundancy signal has a first logic state (logic low) when a same address as one of the fail word line addresses is inputted, and a second logic state (logic high) at the pre-charge interval or when an address different from the fail word line addresses is inputted.
摘要翻译：一种半导体存储器件，包括：熔丝控制电路，用于预先在其自己的电路中提供多个故障字线地址，并输出表示输入地址与故障字线地址之一相同的冗余信号;以及正常字线中断信号，用于输入冗余信号并激活指定冗余字线的冗余字线控制器; 以及正常字线控制器，用于激活对应于输入字线地址的字线，该字线响应于正常字线中断信号被操作或中断，其中正常字线中断信号具有第一逻辑状态（逻辑低电平）），或者当与失败字线地址之一相同的地址被输入时，并且当输入正常地址时具有第二逻辑状态（逻辑高），并且冗余信号具有第一逻辑状态（当输入与失败字线地址之一相同的地址时，以及在预充电间隔或当输入与故障字线地址不同的地址的第二逻辑状态（逻辑高）时，逻辑低）。

7. 发明授权

US07149131B2 Semiconductor memory device and internal voltage generating method thereof 有权
标题翻译：半导体存储器件及其内部电压产生方法
公开(公告)号：US07149131B2
公开(公告)日：2006-12-12
申请号：US11024969
申请日：2004-12-30
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C5/14 , G11C11/4074 , G11C11/4076
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active signal and a precharge signal, an internal power voltage generation controlling unit receiving the active signal and the precharge signal for activating an internal power voltage active signal for a predetermined time, a core voltage generation controlling unit receiving the active signal, the precharge signal and the internal power voltage active signal for activating a core voltage active signal for a predetermined time, an internal power voltage generating unit for generating an internal power voltage during the activation period of the internal power voltage active signal; and a core voltage generating unit for generating a core voltage during the activation period of the core voltage active signal.
摘要翻译：半导体存储器件通过保持内部电源电压和核心电压的质量来降低功耗。半导体存储器件在预充电期间充分保持核心电压来降低功耗。该半导体存储装置包括接收外部控制信号以输出有效信号和预充电信号的指令解码器，接收有效信号的内部电源电压产生控制单元和用于激活内部电力电压有源信号预定时间的预充电信号，接收有效信号的核心电压产生控制单元，用于激活核心电压有源信号预定时间的预充电信号和内部电源电压有效信号;内部电源电压产生单元，用于在激活期间内产生内部电源电压内部电源电压有效信号; 以及核心电压产生单元，用于在核心电压有源信号的激活期间产生核心电压。

8. 发明申请

US20060092743A1 Semiconductor memory device and internal voltage generating method thereof 有权
公开(公告)号：US20060092743A1
公开(公告)日：2006-05-04
申请号：US11024969
申请日：2004-12-30
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active signal and a precharge signal, an internal power voltage generation controlling unit receiving the active signal and the precharge signal for activating an internal power voltage active signal for a predetermined time, a core voltage generation controlling unit receiving the active signal, the precharge signal and the internal power voltage active signal for activating a core voltage active signal for a predetermined time, an internal power voltage generating unit for generating an internal power voltage during the activation period of the internal power voltage active signal; and a core voltage generating unit for generating a core voltage during the activation period of the core voltage active signal.

9. 发明申请

US20060050589A1 Power voltage supplier of semiconductor memory device 有权
标题翻译：半导体存储器件的电源供应商
公开(公告)号：US20060050589A1
公开(公告)日：2006-03-09
申请号：US11020244
申请日：2004-12-27
申请人： Jun-Gi Choi , Yong-Kyu Kim
发明人： Jun-Gi Choi , Yong-Kyu Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C5/147
摘要： The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.
摘要翻译：本发明提供一种电源电压供应器，通过采用储层电容器的共用方案，不增加储层电容器的尺寸，稳定地提供无噪声电力电压。半导体存储器件的电源电压供应器包括：用于提供第一电源电压的第一电源电压线; 用于提供第二电源电压的第二电源电压线; 用于稳定地提供第一和第二电源电压的第一储存电容器; 以及储存电容器控制器，用于选择性地将第一储存电容器连接到第一电源电压线或第二电源电压线。

10. 发明申请

US20050237830A1 Redundancy fuse control circuit and semiconductor memory device having the same and redundancy process method 有权
标题翻译：冗余保险丝控制电路和具有相同冗余处理方法的半导体存储器件
公开(公告)号：US20050237830A1
公开(公告)日：2005-10-27
申请号：US11169947
申请日：2005-06-30
申请人： Yong-Kyu Kim , Sang-Hee Kang
发明人： Yong-Kyu Kim , Sang-Hee Kang
IPC分类号： G11C29/00
CPC分类号： G11C29/84 , G11C29/785
摘要： There is provided a semiconductor memory device comprising a fuse control circuit for providing with a plurality of fail word line addresses written in its own circuit in advance and outputting a redundancy signal representing that an input address is the same as one of the fail word line addresses, and a normal word line interruption signal, a redundancy word line controller for inputting the redundancy signal and activating a designated redundancy word line; and a normal word line controller, for activating a word line corresponding to the input word line address, which is operated or interrupted in response to the normal word line interruption signal, wherein the normal word line interruption signal has a first logic state (logic low) at a pre-charge interval or when a same address as one of the fail word line addresses is inputted, and has a second logic state (logic high) when a normal address is inputted, and the redundancy signal has a first logic state (logic low) when a same address as one of the fail word line addresses is inputted, and a second logic state (logic high) at the pre-charge interval or when an address different from the fail word line addresses is inputted.
摘要翻译：提供了一种半导体存储器件，其包括熔丝控制电路，用于提前写入其自身电路中的多个故障字线地址，并输出表示输入地址与故障字线地址之一相同的冗余信号和正常字线中断信号，冗余字线控制器，用于输入冗余信号并激活指定的冗余字线; 以及正常字线控制器，用于激活对应于输入字线地址的字线，该字线响应于正常字线中断信号被操作或中断，其中正常字线中断信号具有第一逻辑状态（逻辑低电平）），或者当与失败字线地址之一相同的地址被输入时，并且当输入正常地址时具有第二逻辑状态（逻辑高），并且冗余信号具有第一逻辑状态（当输入与失败字线地址之一相同的地址时，以及在预充电间隔或当输入与故障字线地址不同的地址的第二逻辑状态（逻辑高）时，逻辑低）。

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