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1. 发明申请

US20170288634A1 NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING THE SAME 审中-公开
公开(公告)号：US20170288634A1
公开(公告)日：2017-10-05
申请号：US15408730
申请日：2017-01-18
申请人： DAE-WOON KANG , Jeong-Don IHM , Byung-Hoon JEONG , Young-Don CHOI
发明人： DAE-WOON KANG , Jeong-Don IHM , Byung-Hoon JEONG , Young-Don CHOI
IPC分类号： H03H7/38 , G11C16/10 , G11C16/08 , G11C16/26
CPC分类号： H03H7/38 , G11C5/025 , G11C5/04 , G11C7/1057 , G11C7/1084 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/022 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/105 , H03K19/0005 , H03K19/017545
摘要： A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

2. 发明授权

US08307885B2 Cooling apparatus for electronic device 有权
标题翻译：电子设备冷却装置
公开(公告)号：US08307885B2
公开(公告)日：2012-11-13
申请号：US12390201
申请日：2009-02-20
申请人： Ye-Yong Kim , Young-Don Choi
发明人： Ye-Yong Kim , Young-Don Choi
IPC分类号： F28D15/00 , F25B9/02
CPC分类号： F25B9/04 , F25B2500/01 , F28D15/02 , F28D15/0266 , F28D2021/0031 , F28F13/12
摘要： The present invention relates to a cooling apparatus for an electronic device. In the present invention, a coolant passing through a condenser 10 is introduced into and s filled in a compensator 15. The coolant passing through the compensator 15 is introduced into a vaporizer 20 and vaporized through heat exchange with an auxiliary heat source H2 provided outside of the vaporizer. In addition, a vaporizing unit 22 made of a porous material is provided in the vaporizer 20. The coolant passing through the vaporizer 20 and a liquid coolant supplied from the condenser 10 are mixed in a vortex generating unit 30 to form a coolant spray, and the coolant spray moves along a spiral trajectory to be formed into a vortex. Meanwhile, the coolant spray of a vortex is injected to be in close contact with the inner wall of an evaporator 50 to be heat-exchanged with a main heat source H1 positioned outside of the evaporator, thereby cooling the main heat source H1. According to the present invention as mentioned above, the main heat source adjacent to the evaporator is heat-exchanged with the coolant more actively to thereby improve the cooling performance of the electronic device. Also, a pressure loss of the coolant spouted from the venturi tube is further reduced.
摘要翻译：本发明涉及电子设备的冷却装置。在本发明中，通过冷凝器10的冷却剂被引入并填充在补偿器15中。通过补偿器15的冷却剂被引入蒸发器20中，并通过与外部设置的辅助热源H2的热交换而蒸发蒸发器。此外，在蒸发器20中设置由多孔材料制成的蒸发单元22.通过蒸发器20的冷却剂和从冷凝器10供应的液体冷却剂在涡流发生单元30中混合以形成冷却剂喷雾，并且冷却剂喷雾沿着螺旋轨迹移动以形成涡流。同时，将涡流的冷却剂喷雾注入与蒸发器50的内壁紧密接触，以与位于蒸发器外部的主热源H1进行热交换，从而冷却主热源H1。根据如上所述的本发明，与蒸发器相邻的主热源更积极地与冷却剂进行热交换，从而提高电子设备的冷却性能。此外，从文丘里管喷出的冷却剂的压力损失进一步降低。

3. 发明申请

US20120064827A1 SEMICONDUCTOR DEVICE INCLUDING COUPLING CONDUCTIVE PATTERN 有权
标题翻译：包括连接导电图案的半导体器件
公开(公告)号：US20120064827A1
公开(公告)日：2012-03-15
申请号：US13229193
申请日：2011-09-09
申请人： Yong-Hoon KIM , Jong-Joo Lee , Sang-Youb Lee , Young-Don Choi , Hee-Seok Lee
发明人： Yong-Hoon KIM , Jong-Joo Lee , Sang-Youb Lee , Young-Don Choi , Hee-Seok Lee
IPC分类号： H04B5/00
CPC分类号： H01L23/645 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/1023 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H01L2924/3511 , H04B5/0012 , H04B5/0031 , H04B5/0037 , H04B5/0075 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.
摘要翻译：公开了一种包括通孔的半导体器件。半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电模式。可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

4. 发明授权

US08116417B2 Deskewing method and apparatus, and data reception apparatus using the deskewing method and apparatus 有权
标题翻译：脱色方法和装置以及使用该偏移校正方法和装置的数据接收装置
公开(公告)号：US08116417B2
公开(公告)日：2012-02-14
申请号：US12820824
申请日：2010-06-22
申请人： Young-don Choi
发明人： Young-don Choi
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033 , H04L7/0337
摘要： An up/down detection unit samples a received data signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions, wherein the data sampling clock signal, the first edge sampling clock signal, and the second edge sampling clock signal are sequentially activated. A lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area. An upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area. A phase detection unit determines a delay amount indicating the amount by which the data signal is to be delayed according to the upper limit and lower limit detected. A buffer unit delays the data signal by the delay amount determined by the phase detection unit.
摘要翻译：上/下检测单元对接收到的数据信号进行采样，并确定数据信号的第一至第三区域中的哪个数据信号的逻辑电平转换，其中数据采样时钟信号，第一边沿采样时钟信号和第二边沿采样时钟信号被依次激活。如果数据信号的逻辑电平在第一区域中转变，则下限检测单元检测第一区域的下限。如果数据信号的逻辑电平在第三区域中转变，则上限检测单元检测第三区域的上限。相位检测单元根据检测到的上限和下限来确定指示数据信号被延迟的量的延迟量。缓冲单元将数据信号延迟由相位检测单元确定的延迟量。

5. 发明授权

US08053882B2 Stacked semiconductor devices and signal distribution methods thereof 有权
标题翻译：叠层半导体器件及其信号分配方法
公开(公告)号：US08053882B2
公开(公告)日：2011-11-08
申请号：US12801012
申请日：2010-05-17
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , G06F1/10 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique.
摘要翻译：堆叠的半导体器件包括多个堆叠的芯片，每个堆叠的芯片具有用于接收信号的多个元件。用于接收信号的至少一个第一梯形主信号线布置成通过芯片。至少一个第二梯形图主信号线被布置成穿过芯片。多个梯形缓冲器将从第一梯形图主信号线施加的信号缓冲到第二梯形图主信号线。使用梯形电路网络技术将信号均匀分布到堆叠芯片。

6. 发明授权

US07960984B2 Semiconductor device having ESD protection circuit and method of testing the same 有权
标题翻译：具有ESD保护电路的半导体器件及其测试方法
公开(公告)号：US07960984B2
公开(公告)日：2011-06-14
申请号：US12232592
申请日：2008-09-19
申请人： Young-Don Choi , Hoe-Ju Chung
发明人： Young-Don Choi , Hoe-Ju Chung
IPC分类号： G01R31/3187
CPC分类号： G01R31/2884 , H01L23/60 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an electrostatic discharge (ESD) protection circuit and a method of testing the same may provided. The semiconductor device may include one or more stacked chips, each stacked chip may include a test circuit configured to output a test control signal and a selection control signal in response to a test enable signal, an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal, at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal, at least one test pad configured to receive the selected test signal, and at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally.
摘要翻译：可以提供具有静电放电（ESD）保护电路的半导体器件及其测试方法。半导体器件可以包括一个或多个堆叠的芯片，每个堆叠的芯片可以包括测试电路，其被配置为响应于测试使能信号输出测试控制信号和选择控制信号，内部电路被配置为执行操作并输出响应于测试控制信号的多个测试信号，至少一个多路复用器（MUX），被配置为基于选择控制信号选择并输出多个测试信号中的一个;至少一个测试板，被配置为接收所选择的测试信号以及至少一个静电放电（ESD）保护电路，其被配置为从外部排出通过测试焊盘施加的静电。

7. 发明授权

US07928785B2 Loop filter, phase-locked loop, and method of operating the loop filter 有权
标题翻译：环路滤波器，锁相环路和环路滤波器的操作方法
公开(公告)号：US07928785B2
公开(公告)日：2011-04-19
申请号：US12267116
申请日：2008-11-07
申请人： Young-don Choi , Hoon Lee
发明人： Young-don Choi , Hoon Lee
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03L7/0893 , H03L7/0891 , H03L7/093
摘要： A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty control clock signal of which an activation section is shorter than an inactivation section, by controlling a duty of an input clock signal. The variable capacitor unit is charged by an input current and has a capacitance that varies according to the duty control clock signal. The variable capacitor unit may include a switch, a first capacitor, and a second capacitor. The switch is turned on or off in response to the duty control clock signal. The first capacitor is serially connected to the switch and charged by the input current when the switch is turned on. The second capacitor is connected in parallel to the switch and the first capacitor and charged by the input current.
摘要翻译：提供了能够控制电荷共享时间点的环路滤波器，锁相环以及环路滤波器的操作方法。环路滤波器包括占空比控制单元和可变电容器单元。占空比控制部通过控制输入时钟信号的占空比，生成启动部比灭活部短的占空比控制时钟信号。可变电容器单元由输入电流充电并且具有根据占空比控制时钟信号而变化的电容。可变电容器单元可以包括开关，第一电容器和第二电容器。响应于占空比控制时钟信号，开关导通或关断。当开关打开时，第一个电容器串联连接到开关并由输入电流充电。第二电容器并联连接到开关和第一个电容器，并由输入电流充电。

8. 发明申请

US20110031601A1 STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF 有权
标题翻译：堆叠式半导体器件及其串联路径的形成方法
公开(公告)号：US20110031601A1
公开(公告)日：2011-02-10
申请号：US12906592
申请日：2010-10-18
申请人： Young-Don Choi
发明人： Young-Don Choi
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/06 , H01L24/14 , H01L24/17 , H01L2224/0401 , H01L2224/0615 , H01L2224/1416 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/01021 , H01L2924/01033 , H01L2924/01058 , H01L2924/01082 , H01L2924/01322 , H01L2924/30107
摘要： A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed.
摘要翻译：提供叠层半导体器件和形成层叠半导体器件的串行路径的方法。叠层半导体器件包括多个芯片，每个芯片具有用于接收输入信号的第一内部电路，执行指定的操作并输出输出信号。每个芯片包括设置在每个芯片的一个表面上的相同位置处的串行凸块，接收输入信号并将输入信号传送到第一内部电路，以及串联穿通硅通孔（TSV）相对于芯片的中心与串联凸起对称的位置以穿透芯片，以及接收和传送输出信号。这里，芯片交替地旋转和堆叠，使得相邻芯片的串行TSV和串联凸块彼此接触。根据叠层半导体器件和方法，具有相同图案的多个芯片围绕芯片的中心旋转并堆叠，从而可以形成平行路径和串行路径。

9. 发明申请

US20100260299A1 DESKEWING METHOD AND APPARATUS, AND DATA RECEPTION APPARATUS USING THE DESKEWING METHOD AND APPARATUS 有权
标题翻译：使用方法和装置的装置和装置以及数据接收装置
公开(公告)号：US20100260299A1
公开(公告)日：2010-10-14
申请号：US12820824
申请日：2010-06-22
申请人： Young-don Choi
发明人： Young-don Choi
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H04L7/0337
摘要： Deskewing method and apparatus, and a data reception apparatus using the deskewing method and apparatus, in which the deskewing apparatus includes an up/down detection unit, a lower limit detection unit, an upper limit detection unit, a phase detection unit, and a buffer unit. The up/down detection unit samples a received data signal in response to a data sampling clock signal, a first edge sampling clock signal, and a second edge sampling clock signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions by using the result of the sampling, wherein the data sampling clock signal, the first edge sampling clock signal, and the second edge sampling clock signal are sequentially activated. The lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area. The upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area. The phase detection unit determines a delay amount indicating the amount by which the data signal is to be delayed according to the upper limit detected by the upper limit detection unit and the lower limit detected by the lower limit detection unit. The buffer unit delays the data signal by the delay amount determined by the phase detection unit. The deskewing apparatus can optimize data sampling by efficiently reducing data skew. In addition, the deskewing apparatus can minimize data restoration errors by reducing an accumulation of jitter.
摘要翻译：偏移校正方法和装置以及使用该偏移校正方法和装置的数据接收装置，其中该偏移校正装置包括上/下检测单元，下限检测单元，上限检测单元，相位检测单元和缓冲器单元。上/下检测单元响应于数据采样时钟信号，第一边沿采样时钟信号和第二边缘采样时钟信号对接收到的数据信号进行采样，并确定数据信号的第一至第三区域中的哪一个是逻辑电平通过使用采样的结果进行数据信号转换，其中数据采样时钟信号，第一边沿采样时钟信号和第二边缘采样时钟信号被顺序地激活。如果数据信号的逻辑电平在第一区域中转变，则下限检测单元检测第一区域的下限。如果数据信号的逻辑电平在第三区域中转变，则上限检测单元检测第三区域的上限。相位检测单元根据由上限检测单元检测到的上限和由下限检测单元检测到的下限来确定表示数据信号要延迟的量的延迟量。缓冲单元将数据信号延迟由相位检测单元确定的延迟量。去歪斜设备可以通过有效减少数据偏移来优化数据采样。此外，通过减少抖动的累积，该脱色设备可以最小化数据恢复错误。

10. 发明授权

US07659785B2 Voltage controlled oscillator and PLL having the same 有权
标题翻译：压控振荡器和PLL具有相同的功能
公开(公告)号：US07659785B2
公开(公告)日：2010-02-09
申请号：US11769114
申请日：2007-06-27
申请人： Jung Sunwoo , Young-Don Choi
发明人： Jung Sunwoo , Young-Don Choi
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03L7/0995 , H03L2207/06
摘要： A Voltage Controlled Oscillator (VCO) includes a plurality of oscillation units connected in cascade to form a chain; and a plurality of current source sections operatively connected to the oscillation units, the current source sections each being configured to control current provided to the oscillation units, wherein each of the current source sections includes: at least one fixed current source configured to perform a current control of a corresponding oscillation unit by using a fixed voltage; and at least one variable current source configured to perform a current control of the corresponding oscillation unit by using a variable voltage.
摘要翻译：压控振荡器（VCO）包括串联连接以形成链的多个振荡单元; 以及可操作地连接到所述振荡单元的多个电流源部分，所述电流源部分被配置为控制提供给所述振荡单元的电流，其中每个电流源部分包括：至少一个固定电流源，被配置为执行电流通过使用固定电压控制相应的振荡单元; 以及至少一个可变电流源，被配置为通过使用可变电压来执行对应的振荡单元的电流控制。

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