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1. 发明授权

US08914709B1 Manufacturing testing for LDPC codes 有权
标题翻译： LDPC码制造测试
公开(公告)号：US08914709B1
公开(公告)日：2014-12-16
申请号：US13041218
申请日：2011-03-04
申请人： Yu Kou , Lingqi Zeng , Jason Bellorado , Marcus Marrow
发明人： Yu Kou , Lingqi Zeng , Jason Bellorado , Marcus Marrow
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , G06F11/08 , G06F11/1012 , G11C29/56004 , H03M13/015 , H03M13/1102 , H03M13/154
摘要： A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.
摘要翻译：存储系统包括信道检测器，LDPC解码器和擦除块。信道检测器被配置为接收对应于从存储器读取的数据的数据并输出LLR信号。 LDPC解码器被配置为接收LLR信号并将反馈信号输出到信道检测器。擦除块被配置为擦除LLR信号和反馈信号中的至少一个的一部分。一种测试方法包括产生与擦除模式对应的错误率函数。该函数是多次LDPC迭代的函数。该方法包括至少部分地基于错误率函数来确定测试参数，其中测试参数包括LDPC迭代的测试次数，通过错误率和擦除模式。该方法包括使用测试参数测试存储设备。

2. 发明授权

US08898546B1 Error recovery using erasures for NAND flash 有权
标题翻译：使用NAND闪存的擦除进行错误恢复
公开(公告)号：US08898546B1
公开(公告)日：2014-11-25
申请号：US13607302
申请日：2012-09-07
申请人： Yu Kou , Xiangyu Tang
发明人： Yu Kou , Xiangyu Tang
IPC分类号： G11C29/00 , H03M11/00 , G01R31/30
CPC分类号： G06F11/1068 , G06F11/1012 , G11C29/52 , G11C2029/0411 , H03M13/1105 , H03M13/152 , H03M13/373 , H03M13/3738 , H03M13/3746 , H03M13/455
摘要： Data is processed by selecting one or more bits in a codeword to replace with an erasure. The selected bits in the codeword are replaced with the erasure and error correction decoding is performed on the codeword with the erasure in place for the selected bits.
摘要翻译：通过选择代码字中的一个或多个位来替换数据来进行擦除。码字中所选择的比特被擦除代替，并且对于所选择的比特，针对码字执行了纠错解码，而擦除就位。

3. 发明授权

US08631311B1 Data recovery using existing reconfigurable read channel hardware 有权
标题翻译：使用现有的可重新配置的读通道硬件进行数据恢复
公开(公告)号：US08631311B1
公开(公告)日：2014-01-14
申请号：US13453729
申请日：2012-04-23
申请人： Kai Keung Chan , Yu Kou , Xin-Ning Song , Wing Hui
发明人： Kai Keung Chan , Yu Kou , Xin-Ning Song , Wing Hui
IPC分类号： G06F11/00
CPC分类号： H04L1/0045 , H04L1/0057
摘要： A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.
摘要翻译：公开了一种恢复数据的方法。感测的模拟信号使用模数转换器（ADC）转换成数字采样。使用第一滤波器将数字样本处理成经处理的数字样本。经处理的数字样本被解码成解码数据。然后确定解码数据是否可接受。使用再处理电路将经处理的数字样本反馈到第一滤波器，使得在解码数据不可接受的情况下，经处理的数字样本被重新处理成再处理的数字样本。提供一组再处理系数用于第一滤波器以重新处理经处理的数字样本。

4. 发明授权

US08572463B2 Quasi-cyclic LDPC encoding and decoding for non-integer multiples of circulant size 有权
标题翻译：用于循环大小非整数倍的准循环LDPC编码和解码
公开(公告)号：US08572463B2
公开(公告)日：2013-10-29
申请号：US13035770
申请日：2011-02-25
申请人： Lingqi Zeng , Yu Kou , Kin Man Ng , Kwok W. Yeung
发明人： Lingqi Zeng , Yu Kou , Kin Man Ng , Kwok W. Yeung
IPC分类号： G11C29/00
CPC分类号： H03M13/1111 , H03M13/116 , H03M13/3994
摘要： In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the unpadded data over the decision and reliability information corresponding to the unpadded data during message passing. Zero padding is removed from the decoded data.
摘要翻译：在处理准循环低密度奇偶校验（QC-LDPC）数据时，接收到包括与非附加数据相对应的判定和可靠性信息的输入信号。与填充数据相对应的判定和可靠性信息被引入到输入信号中。执行消息传递一次或多次以获得解码数据。这包括使用（1）对应于未附加数据的决策和可靠性信息，以及（2）与填充数据相对应的决策和可靠性信息，其中优先考虑与决定有关的未附加数据的决策和可靠性信息以及在消息传递期间对应于未附加数据的可靠性信息。从解码数据中删除零填充。

5. 发明申请

US20110208981A1 CURRENT LIMITING AND AVERAGING CIRCUIT AND PERIPHERAL DEVICE AND COMPUTER SYSTEM USING THE SAME 有权
标题翻译：电流限制和平均电路和外围设备和使用它的计算机系统
公开(公告)号：US20110208981A1
公开(公告)日：2011-08-25
申请号：US12874127
申请日：2010-09-01
申请人： Fang-Yu Kou , Jui-Hui Lin , Jui-I Wu , Hung-Jen Hou
发明人： Fang-Yu Kou , Jui-Hui Lin , Jui-I Wu , Hung-Jen Hou
IPC分类号： G06F1/26 , G06F13/12
CPC分类号： G06F1/266
摘要： A current limiting and averaging circuit for driving a peripheral core circuit with a lower limit current value in response to a supply signal, includes a current limiting module, an energy storage module, and a converter module. The current limiting module provides a limited supply signal whose current value is smaller than or equal to an upper limit value according to the supply signal. The energy storage module stores a storage signal according to the limited supply signal when the upper limit value is higher than the lower limit current value and provides a discharge signal according to the storage signal when the upper limit value is lower than the lower limit current value. The converter module provides a driving signal for driving the peripheral core circuit in response to the limited supply signal or the limited supply signal and the discharge signal.
摘要翻译：用于响应于电源信号驱动具有下限电流值的外围核心电路的限流和平均电路包括限流模块，能量存储模块和转换器模块。电流限制模块根据电源信号提供电流值小于或等于上限值的有限电源信号。当上限值高于下限电流值时，能量存储模块根据受限供电信号存储存储信号，并且当上限值低于下限电流值时，根据存储信号提供放电信号。转换器模块响应于限制的电源信号或限制的电源信号和放电信号提供用于驱动外围核心电路的驱动信号。

6. 发明授权

US07388932B1 Fully parallel multi-channel demodulator 有权
标题翻译：全并行多通道解调器
公开(公告)号：US07388932B1
公开(公告)日：2008-06-17
申请号：US10335209
申请日：2002-12-30
申请人： WeiMin Zhang , Vladimir Radionov , Roger Stenerson , Bin-Fan Liu , Yu Kou
发明人： WeiMin Zhang , Vladimir Radionov , Roger Stenerson , Bin-Fan Liu , Yu Kou
IPC分类号： H03K9/00
CPC分类号： H04L27/0012 , H04L1/004 , H04L7/0079 , H04L25/03006
摘要： An improved multi-channel demodulator is provided. The improved demodulator includes an automatic gain control, a data buffer and a demodulation engine. Data from various RF channels are processed by the automatic gain control in order to keep the data at their respective constant levels. Output from the automatic gain control is passed to the data buffer for storage. Corresponding data from a selected channel is then processed by the demodulation engine. The improved demodulator is able to operate in any one of three operating modes, namely, a data processing mode, a channel switching mode and a waiting mode. In the data processing mode, the demodulation engine processes the channel data that is currently loaded into the demodulation engine. In the channel switching mode, the demodulation engine stores the current channel data into the data buffer and retrieves and loads channel data from another channel for processing. In addition, status and history information relating to the current channel data is stored into a channel status memory and status and history information relating to the next channel to be processed is retrieved from the channel status memory. In one exemplary aspect, in order to reduce the channel switching time, status and history information relating to the next channel to be processed is preloaded during the previous data processing mode. In the waiting mode, the demodulation engine awaits further processing instructions to decide whether to enter into either the data processing mode or the channel switching mode.
摘要翻译：提供改进的多通道解调器。改进的解调器包括自动增益控制，数据缓冲器和解调引擎。来自各种RF信道的数据由自动增益控制处理，以便将数据保持在它们各自的恒定水平。自动增益控制的输出传递到数据缓冲区进行存储。然后由解调引擎处理来自选定信道的对应数据。改进的解调器能够以三种操作模式中的任一种操作，即数据处理模式，信道切换模式和等待模式。在数据处理模式中，解调引擎处理当前加载到解调引擎中的信道数据。在信道切换模式中，解调引擎将当前信道数据存储到数据缓冲器中，并从另一个信道检索和加载信道数据进行处理。此外，与当前频道数据相关的状态和历史信息被存储到频道状态存储器中，并且从频道状态存储器检索与要处理的下一频道有关的状态和历史信息。在一个示例性方面，为了减少频道切换时间，在先前的数据处理模式期间预先加载与要处理的下一频道相关的状态和历史信息。在等待模式中，解调引擎等待进一步的处理指令来决定是进入数据处理模式还是进入信道切换模式。

7. 发明授权

US08918696B2 Implementation of LDPC selective decoding scheduling 有权
标题翻译： LDPC选择性解码调度的实现
公开(公告)号：US08918696B2
公开(公告)日：2014-12-23
申请号：US13084022
申请日：2011-04-11
申请人： Kin Man Ng , Kwok W. Yeung , Lingqi Zeng , Yu Kou , Aditi R. Ganesan
发明人： Kin Man Ng , Kwok W. Yeung , Lingqi Zeng , Yu Kou , Aditi R. Ganesan
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/114 , H03M13/116
摘要： A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group.
摘要翻译：公开了一种解码数据的方法。该方法包括将低密度奇偶校验（LDPC）矩阵划分成多个组，每个组包括一个或多个校验节点层。该方法还包括至少部分地基于成本函数来选择组中的一个，所述成本函数至少部分地基于与变量节点相关联的信息或与校验节点相关联的信息，或两者。该方法还包括对所选择的组执行LDPC分层解码。

8. 发明授权

US08843812B1 Buffer management in a turbo equalization system 有权
标题翻译： turbo均衡系统中的缓冲区管理
公开(公告)号：US08843812B1
公开(公告)日：2014-09-23
申请号：US13489122
申请日：2012-06-05
申请人： Xiangyu Tang , Yu Kou , Lingqi Zeng
发明人： Xiangyu Tang , Yu Kou , Lingqi Zeng
IPC分类号： H03M13/03 , H03M13/00 , H03M13/41 , H03M13/29
CPC分类号： H03M13/2963 , G06F11/10 , H03M13/1111 , H03M13/1125 , H03M13/1128 , H03M13/2957 , H03M13/413 , H03M13/4138 , H03M13/6331
摘要： A plurality of metrics associated with a plurality of partially decoded codewords is obtained. The plurality of partially decoded codewords has been processed at least once by a first soft output decoder and a second soft output decoder and the plurality of partially decoded codewords is stored in a memory. At least one of the plurality of partially decoded codewords is selected based at least in part on the plurality of metrics; the memory is instructed to vacate the at least one selected codeword.
摘要翻译：获得与多个部分解码的码字相关联的多个度量。多个部分解码的码字已被第一软输出解码器和第二软输出解码器处理至少一次，并且多个部分解码的码字被存储在存储器中。至少部分地基于所述多个度量来选择所述多个部分解码的码字中的至少一个; 指示存储器腾出至少一个所选择的码字。

9. 发明授权

US08677218B2 LDPC decoding with on the fly error recovery 有权
标题翻译： LDPC解码与即时错误恢复
公开(公告)号：US08677218B2
公开(公告)日：2014-03-18
申请号：US12953348
申请日：2010-11-23
申请人： Lingqi Zeng , Yu Kou
发明人： Lingqi Zeng , Yu Kou
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , G11B20/10296 , G11B20/1833 , G11B2020/185 , G11B2220/2508 , H03M13/1111 , H03M13/2957 , H03M13/4138 , H03M13/6343 , H03M13/6583
摘要： It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed using the decoder and the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed using the decoder and the data associated with the decoder.
摘要翻译：决定是否调整与解码器相关联的数据。在决定调整与解码器相关联的数据的情况下，调整数据以获得调整后的数据，并使用解码器和调整后的数据进行解码。在决定不调整与解码器相关联的数据的情况下，使用解码器和与解码器相关联的数据来执行解码。

10. 发明授权

US08504894B1 Systematic encoding for non-full row rank, quasi-cyclic LDPC parity check matrices 有权
标题翻译：非全行排序，准循环LDPC奇偶校验矩阵的系统编码
公开(公告)号：US08504894B1
公开(公告)日：2013-08-06
申请号：US13039040
申请日：2011-03-02
申请人： Lingqi Zeng , Yu Kou , Kin Man Ng , Kwok W. Yeung
发明人： Lingqi Zeng , Yu Kou , Kin Man Ng , Kwok W. Yeung
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/611 , H03M13/618 , H03M13/6356 , H03M13/6502
摘要： Encoding is performed by putting a low-density parity-check (LDPC) generator matrix into partial quasi-cyclic form comprising an identity matrix, a parity generator matrix, a zero matrix and a remainder matrix. The parity generator matrix is quasi-cyclic and the remainder matrix is not quasi-cyclic. An encoder is used to generate LDPC encoded data using the parity generator matrix and without using the remainder matrix.
摘要翻译：通过将低密度奇偶校验（LDPC）生成器矩阵置于包括单位矩阵，奇偶校验生成矩阵，零矩阵和余数矩阵的部分准循环形式中来执行编码。奇偶生成矩阵是准循环的，剩余矩阵不是准循环的。编码器用于使用奇偶校验发生器矩阵生成LDPC编码数据，而不使用余数矩阵。

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