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1. 发明申请

US20170163379A1 WIRELESS COMMUNICATION DEVICE AND METHOD 审中-公开
公开(公告)号：US20170163379A1
公开(公告)日：2017-06-08
申请号：US15434237
申请日：2017-02-16
申请人： HITACHI KOKUSAI ELECTRIC INC.
发明人： Kei ITO
IPC分类号： H04L1/00 , H04L27/34 , H04L27/18 , H04L25/03
CPC分类号： H04L1/0041 , H03M13/27 , H03M13/2792 , H03M13/3723 , H03M13/4138 , H03M13/45 , H03M13/612 , H03M13/6508 , H04L1/0047 , H04L1/005 , H04L1/0071 , H04L25/03891 , H04L27/0008 , H04L27/18 , H04L27/22 , H04L27/34 , H04L27/38
摘要： SISO decoding of a reception signal having a scrambled symbol arrangement is realized using a process having reduced complexity. Coordinates are generated for a reference point obtained by scrambling and mapping a symbol number not a symbol reference point position. This reference point simulates transmission-side scrambling and is generated for each symbol number by a first mapping unit. Because the binary expression of a corresponding original signal number is retained, a bit likelihood calculation unit can easily calculate a bit likelihood based on the distance between the reference point and a reception signal. The calculated bit likelihood is then deinterleaved and subjected to SISO error-correcting decoding. The thus obtained bit likelihood is then reinterleaved and used to calculate a symbol probability. Soft symbols are generated through the multiplication of all the calculated symbol probabilities by corresponding reference points output by a second mapping unit similar to the first mapping unit.

2. 发明授权

US09438276B2 Method and apparatus for improved performance of iterative decoders on channels with memory 有权
标题翻译：用于改善具有存储器的通道上的迭代解码器性能的方法和装置
公开(公告)号：US09438276B2
公开(公告)日：2016-09-06
申请号：US13674767
申请日：2012-11-12
申请人： Marvell International Ltd.
发明人： Nedeljko Varnica , Nitin Nangare , Gregory Burd , Zining Wu
IPC分类号： H03M13/00 , H03M13/11 , H03M13/29 , H03M13/39 , H03M13/41
CPC分类号： H03M13/6331 , H03M13/1105 , H03M13/2957 , H03M13/3905 , H03M13/4138
摘要： Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.
摘要翻译：公开了用于改善具有存储器的各种通道上的迭代解码器的性能的系统和方法。这些系统和方法可以减少迭代解码器不能产生与最初在通信或数据存储系统中发送的数据匹配的解码数据的情况的频率或数量。迭代解码器包括SISO信道检测器和ECC解码器，并且按照常规解码模式中的至少一个迭代解码算法和/或错误恢复模式中的至少一个迭代解码算法解码编码信息。

3. 发明授权

US09362933B1 Noise-predictive detector adaptation with corrected data 有权
标题翻译：具有校正数据的噪声预测检测器适配
公开(公告)号：US09362933B1
公开(公告)日：2016-06-07
申请号：US13546859
申请日：2012-07-11
申请人： Panu Chaichanavong
发明人： Panu Chaichanavong
IPC分类号： H03D1/00 , H03M1/08
CPC分类号： H03M13/3961 , H03M1/08 , H03M13/1111 , H03M13/2957 , H03M13/4138 , H03M13/4146 , H03M13/6325 , H04L1/0045 , H04L1/005 , H04L1/0054
摘要： The present disclosure includes apparatus, systems, and techniques relating to noise-predictive detector adaptation. A described technique includes operating a decoder to decode a received encoded signal based on estimation parameters to produce paths including a first path and a second path, the second path being an alternate to the first path, determining a decoded path based on at least a portion of the paths, determining a winning path of the first path and the second path based on whether the decoded path matches the first path or the second path, and updating the estimation parameters based on one or more error terms and the winning path to favor selection of the winning path by the decoder and to disfavor selection of a losing path of the first and second paths by the decoder in a subsequent iteration.
摘要翻译：本公开包括与噪声预测检测器适配相关的装置，系统和技术。所描述的技术包括操作解码器以基于估计参数对接收到的编码信号进行解码以产生包括第一路径和第二路径的路径，第二路径是第一路径的替代，基于至少一部分来确定解码路径的路径，基于解码路径是否匹配第一路径或第二路径，确定第一路径和第二路径的获胜路径，以及基于一个或多个错误项和获胜路径更新估计参数以有利于选择并且解码器在后续迭代中不利地选择第一和第二路径的丢失路径。

4. 发明授权

US09112539B2 Systems and methods for iterative data processing using feedback iteration 有权
标题翻译：使用反馈迭代迭代数据处理的系统和方法
公开(公告)号：US09112539B2
公开(公告)日：2015-08-18
申请号：US13654417
申请日：2012-10-18
申请人： LSI Corporation
发明人： Fan Zhang
IPC分类号： H03M13/00 , H03M13/05 , H03M13/29 , H03M13/37 , H03M13/11 , H03M13/41
CPC分类号： H03M13/658 , H03M13/1111 , H03M13/2957 , H03M13/3723 , H03M13/4138 , H03M13/6337 , H03M13/6343
摘要： Systems and methods for data processing. In one case, a data processing system includes a data detector circuit configured to apply a data detection algorithm to a detector input to yield a second detected output, and a data decoder circuit configured to apply a data decoding algorithm to a decoder input to yield a decoded output. The decoder input is derived from an interim data set calculated as a combination of at least a first detected output and the second detected output.
摘要翻译：用于数据处理的系统和方法。在一种情况下，数据处理系统包括：数据检测器电路，被配置为将数据检测算法应用于检测器输入以产生第二检测输出;以及数据解码器电路，被配置为将数据解码算法应用于解码器输入，以产生解码输出。解码器输入是从作为至少第一检测输出和第二检测输出的组合计算的中间数据集导出的。

5. 发明授权

US09105301B2 Signal processing apparatus, signal processing method, and magnetic disk apparatus 有权
标题翻译：信号处理装置，信号处理方法以及磁盘装置
公开(公告)号：US09105301B2
公开(公告)日：2015-08-11
申请号：US13559947
申请日：2012-07-27
申请人： Nobuhiro Maeto
发明人： Nobuhiro Maeto
IPC分类号： G11B5/035 , G11B20/10 , H03M13/41 , H03M13/00
CPC分类号： G11B20/10 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10268 , G11B20/10296 , G11B2220/2508 , H03M13/4107 , H03M13/4138 , H03M13/6577
摘要： According to at least one embodiment, a signal processor apparatus includes a Viterbi decoder, a processor, and an adjustment module. The Viterbi decoder calculates a branch metric based on an input signal. The processor outputs a processing result correlated with a processing result of the Viterbi decoder. A latency of the processor for the input signal is lower than a latency of the Viterbi decoder. The adjustment module adjusts a first parameter for calculating the branch metric based on the processing result of the processor.
摘要翻译：根据至少一个实施例，信号处理器装置包括维特比解码器，处理器和调整模块。维特比解码器基于输入信号计算分支度量。处理器输出与维特比解码器的处理结果相关的处理结果。输入信号的处理器的延迟低于维特比解码器的等待时间。调整模块基于处理器的处理结果调整用于计算分支度量的第一参数。

6. 发明授权

US08996970B2 Systems and methods for positive feedback short media defect detection 有权
标题翻译：正反馈短介质缺陷检测的系统和方法
公开(公告)号：US08996970B2
公开(公告)日：2015-03-31
申请号：US13659795
申请日：2012-10-24
申请人： LSI Corporation
发明人： Fan Zhang , Weijun Tan , Shaohua Yang
IPC分类号： G06F11/00 , G06F11/08 , H03M13/29 , H03M13/37 , H03M13/00 , H03M13/11 , H03M13/41
CPC分类号： G06F11/08 , G11B20/18 , G11B20/1883 , H03M13/1111 , H03M13/2957 , H03M13/3723 , H03M13/4138 , H03M13/6337 , H03M13/6343 , H03M13/658
摘要： Various systems and methods for media defect detection.
摘要翻译：用于介质缺陷检测的各种系统和方法。

7. 发明申请

US20150026541A1 Iterative Decoding for Cascaded LDPC and TCM Coding 有权
标题翻译：用于级联LDPC和TCM编码的迭代解码
公开(公告)号：US20150026541A1
公开(公告)日：2015-01-22
申请号：US14336074
申请日：2014-07-21
申请人： NEC Laboratories America, Inc. , NEC Corporation
发明人： Shaoliang Zhang , Fatih Yaman , Yoshihisa Inada , Takaaki Ogata , Takanori Inoue
IPC分类号： H03M13/11 , H03M13/00 , H04L1/00
CPC分类号： H03M13/1111 , H03M13/256 , H03M13/2957 , H03M13/4138 , H04L1/005 , H04L1/0057 , H04L1/006 , H04L1/0064 , H04L1/0076
摘要： At a receiver side, to enhance the performance of concatenated LDPC and TCM coding, an iterative decoding between TCM decoder and LDPC decoder enables improvement in the reliability of received LLRs of each symbol after each iteration. A SOVA output of the TCM is used for LDPC decoding, and then the updated LLRs from LDPC decoder are further looped back to the TCM decoder for the next iteration. In such a manner, the decoding performance could be significantly improved after just several iterations.
摘要翻译：在接收机侧，为了提高级联LDPC和TCM编码的性能，TCM解码器和LDPC解码器之间的迭代解码器能够在每次迭代后提高每个符号的接收LLR的可靠性。 TCM的SOVA输出用于LDPC解码，然后来自LDPC解码器的更新的LLR进一步循环回TCM解码器进行下一次迭代。以这种方式，在几次迭代之后，解码性能可以显着提高。

8. 发明申请

US20140258809A1 SYSTEMS AND METHODS FOR DECODING WITH LATE RELIABILITY INFORMATION 有权
标题翻译：用可靠性信息进行解码的系统和方法
公开(公告)号：US20140258809A1
公开(公告)日：2014-09-11
申请号：US14197408
申请日：2014-03-05
申请人： Marvell World Trade Ltd.
发明人： Dung Viet Nguyen , Shashi Kiran Chilappagari , Phong Sy Nguyen
IPC分类号： H03M13/11
CPC分类号： H03M13/1111 , G06F11/1068 , G11C29/00 , H03M13/1105 , H03M13/1108 , H03M13/116 , H03M13/255 , H03M13/2957 , H03M13/37 , H03M13/3707 , H03M13/4138 , H04L1/005 , H04L1/0052 , H04L1/0057
摘要： Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time. The variable node is decoded using a first decoding scheme after the first time and before the second time, and the variable node is decoded using a second decoding scheme different from the first decoding scheme after the second time.
摘要翻译：提供了解码数据的系统和方法。第一次接收到变量节点的变量节点值，并在第二时间接收到可变节点的可靠性数据。在第一时间之后和第二时间之前，使用第一解码方案对变量节点进行解码，并且在第二次之后，使用与第一解码方案不同的第二解码方案对变量节点进行解码。

9. 发明授权

US08819530B1 Iterative decoder memory arrangement 有权
标题翻译：迭代解码器存储器布置
公开(公告)号：US08819530B1
公开(公告)日：2014-08-26
申请号：US13973880
申请日：2013-08-22
申请人： Marvell International Ltd.
发明人： Engling Yeo , Panu Chaichanavong , Nedeljko Varnica , Gregory Burd , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/2957 , H03M13/4138 , H03M13/6325 , H03M13/6343 , H03M13/6561
摘要： The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes R banks; Q banks; circuitry configured to store R data for a current codeword in a first R bank of the R banks and store R data for a previous codeword in a second R bank of the R banks; circuitry configured to alternate among the R banks for storing current codeword R data; circuitry configured to store Q data for the current codeword in a first Q bank of the Q banks and store Q data for the previous codeword in a second Q bank of the Q banks; and circuitry configured to alternate among the Q banks for storing current codeword Q data. The apparatus can include circuitry configured to interleave read accesses among the R banks.
摘要翻译：本公开包括与迭代解码器存储器布置相关的装置，系统和技术。所描述的装置包括R组; Q银行配置为存储当前码字的R数据在R组的第一R组中的R数据并存储在R组的第二R组中的先前码字的R数据; 配置为在R组之间交替存储当前码字R数据的电路; 电路，被配置为存储所述Q组的第一Q组中当前码字的Q数据，并存储所述Q组的第二Q组中的所述先前码字的Q数据; 以及被配置为在Q组之间交替存储当前码字Q数据的电路。该装置可以包括被配置为在R组之间交错读取访问的电路。

10. 发明授权

US08589774B1 Averaging signals to improve signal interpretation 有权
标题翻译：平均信号以改善信号解读
公开(公告)号：US08589774B1
公开(公告)日：2013-11-19
申请号：US13745655
申请日：2013-01-18
申请人： Hongxin Song , Zining Wu
发明人： Hongxin Song , Zining Wu
IPC分类号： H03M13/03
CPC分类号： H03M13/3738 , G11B20/10027 , G11B20/10037 , G11B20/10046 , G11B20/10175 , G11B20/10277 , G11B20/10305 , G11B20/1037 , G11B20/10527 , G11B20/18 , G11B20/1816 , G11B20/1876 , G11B20/24 , G11B2020/10694 , G11B2020/183 , G11B2220/2516 , H03M5/145 , H03M13/3784 , H03M13/4138
摘要： Systems and techniques to interpret signals on a noisy channel are described. A described technique includes storing a group of signals including a filtered digital signal and one or more previous signals, the filtered digital signal being based on an analog signal; interpreting the filtered digital signal as first discrete values; determining whether the first discrete values are adequately indicated based on a result of the interpreting; initiating a retry mode when the first discrete values are not adequately indicated; producing, in the retry mode, a new signal, the new signal being determined based on an average of at least a portion of the group of signals; interpreting, in the retry mode, the new signal as second discrete values; and determining whether the second discrete values are adequately indicated based on hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal.
摘要翻译：描述了在噪声信道上解释信号的系统和技术。所描述的技术包括存储包括经滤波的数字信号和一个或多个先前信号的一组信号，滤波后的数字信号基于模拟信号; 将经滤波的数字信号解释为第一离散值; 基于所述解释的结果来确定所述第一离散值是否被充分地指示; 当第一离散值未被充分表示时，启动重试模式; 在重试模式下产生一个新信号，该新信号是基于该组信号的至少一部分的平均值来确定的; 在重试模式下将新信号解释为第二离散值; 以及基于由所述新信号指示的硬判决和由所述滤波数字信号指示的硬判决来确定所述第二离散值是否被充分地指示。

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