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1. 发明申请

US20160034106A1 TOUCH APPARATUS AND TOUCH SENSING METHOD THEREOF 审中-公开
标题翻译：触摸装置和触摸感应方法
公开(公告)号：US20160034106A1
公开(公告)日：2016-02-04
申请号：US14583195
申请日：2014-12-26
申请人： Pen-Ning Kuo , Chung-Lung Yang , Yung-Chih Chen
发明人： Pen-Ning Kuo , Chung-Lung Yang , Yung-Chih Chen
IPC分类号： G06F3/042
CPC分类号： G06F3/0325
摘要： A touch apparatus and a touch sensing method thereof are provided. Touch information generated according to received scanning beams is returned by a touch tool, and coordinates of the touch tool on a touch area is calculated according to the returned touch information.
摘要翻译：提供了一种触摸装置及其触摸感测方法。根据接收到的扫描光束生成的触摸信息由触摸工具返回，并且根据返回的触摸信息计算触摸区域上的触摸工具的坐标。

2. 发明授权

US08552961B2 Shift register circuit 有权
标题翻译：移位寄存器电路
公开(公告)号：US08552961B2
公开(公告)日：2013-10-08
申请号：US13106873
申请日：2011-05-13
申请人： Yu-Chung Yang , Yung-Chih Chen
发明人： Yu-Chung Yang , Yung-Chih Chen
IPC分类号： G09G3/36
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/0286 , G09G2320/0252 , G11C19/184 , G11C19/287
摘要： A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.
摘要翻译：移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。每个移位寄存器级包括驱动单元，输入单元，驱动调整单元和下拉单元。驱动单元用于根据系统时钟和驱动控制电压输出门信号。输入单元用于根据输入控制信号和第一输入信号输出驱动控制电压。驱动调整单元用于根据第二输入信号和第三输入信号调整驱动控制电压。下拉单元用于根据第四输入信号来拉下门信号和驱动控制电压。

3. 发明授权

US08456454B2 Display panel 有权
标题翻译：显示面板
公开(公告)号：US08456454B2
公开(公告)日：2013-06-04
申请号：US12488946
申请日：2009-06-22
申请人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
发明人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
IPC分类号： G06F3/038 , G09G5/00 , G02F1/1333
CPC分类号： G09G3/3677 , G09G2300/0426 , G09G2330/08 , G09G2330/12
摘要： A display panel is disclosed, which includes a substrate, a shift register array, plural scan lines, a compensating circuit, a first repair line, and a second repair line. The shift register array having plural shift registers is disposed on a non-display area of the substrate. The scan lines connect to the shift registers respectively to drive plural display units. The first repair line and the second repair line are connected to the compensating circuit and bridged over two ends of each scan line in the non-display area, respectively.
摘要翻译：公开了一种显示面板，其包括基板，移位寄存器阵列，多条扫描线，补偿电路，第一修复线和第二修复线。具有多个移位寄存器的移位寄存器阵列设置在基板的非显示区域上。扫描线分别连接到移位寄存器以驱动多个显示单元。第一修理线和第二修复线分别连接到补偿电路并桥接在非显示区域中的每条扫描线的两端。

4. 发明授权

US08396183B2 Shift register circuit 有权
标题翻译：移位寄存器电路
公开(公告)号：US08396183B2
公开(公告)日：2013-03-12
申请号：US13049863
申请日：2011-03-16
申请人： Yu-Chung Yang , Yung-Chih Chen , Kuo-Hua Hsu , Kuo-Chang Su
发明人： Yu-Chung Yang , Yung-Chih Chen , Kuo-Hua Hsu , Kuo-Chang Su
IPC分类号： G11C19/00
CPC分类号： G09G3/20 , G09G3/3674 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
摘要： A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit, a pull-up unit, a pull-down unit, a control unit and an auxiliary pull-down unit. The input unit is put in use for outputting a driving control voltage according to at least one first input signal. The pull-up unit pulls up a corresponding gate signal according to the driving control voltage and a system clock. The pull-down unit pulls down the corresponding gate signal to a first power voltage according to a control signal. The control unit is utilized for generating the control signal according to the corresponding gate signal. The auxiliary pull-down unit pulls down the driving control voltage to a second power voltage according to a second input signal.
摘要翻译：移位寄存器电路包括用于提供多个门信号的多个移位寄存器级。每个移位寄存器级包括输入单元，上拉单元，下拉单元，控制单元和辅助下拉单元。输入单元被用于根据至少一个第一输入信号输出驱动控制电压。上拉单元根据驱动控制电压和系统时钟提取相应的门信号。下拉单元根据控制信号将相应的门信号拉低至第一电源电压。控制单元用于根据相应的门信号产生控制信号。辅助下拉单元根据第二输入信号将驱动控制电压下拉到第二电源电压。

5. 发明授权

US08350841B2 ESD protection circuit and display apparatus using the same 有权
标题翻译： ESD保护电路及使用其的显示装置
公开(公告)号：US08350841B2
公开(公告)日：2013-01-08
申请号：US13016302
申请日：2011-01-28
申请人： Chia-Sheng Li , Yung-Chih Chen , Chih-Lung Lin
发明人： Chia-Sheng Li , Yung-Chih Chen , Chih-Lung Lin
IPC分类号： G06F3/038 , G09G5/00 , H02H3/20 , H02H9/04 , H02H9/00 , H02H3/22
CPC分类号： G09G3/20 , G09G3/3648 , G09G2330/04
摘要： An ESD protection circuit comprises three transistors and two voltage dividers. The two source/drain terminals of a first transistor are electrically coupled to a first power line and a second power line respectively. The two source/drain terminals of a second transistor are electrically coupled to the first power line and a gate terminal of the first transistor respectively. The two source/drain terminals of a third transistor are electrically coupled to the gate terminal of the first transistor and the second power line respectively. A first voltage divider supplies a first voltage to a gate terminal of the second transistor according to a potential difference between the first power line and the second power line. A second voltage divider supplies a second voltage to a gate terminal of the third transistor according to the potential difference between the first power line and the second power line.
摘要翻译： ESD保护电路包括三个晶体管和两个分压器。第一晶体管的两个源极/漏极端子分别电耦合到第一电力线和第二电力线。第二晶体管的两个源极/漏极端子分别电耦合到第一电源线和第一晶体管的栅极端子。第三晶体管的两个源极/漏极端子分别电耦合到第一晶体管和第二电源线的栅极端子。第一分压器根据第一电力线和第二电力线之间的电位差向第二晶体管的栅极端子提供第一电压。第二分压器根据第一电力线和第二电力线之间的电位差向第三晶体管的栅极端子提供第二电压。

6. 发明授权

US08175215B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08175215B2
公开(公告)日：2012-05-08
申请号：US12572247
申请日：2009-10-01
申请人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
发明人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.
摘要翻译：移位寄存器包括多个级联连接级。每一级响应于时钟信号和第一控制信号产生输出信号。每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。上拉模块用于根据时钟信号提供输出信号。上拉驱动模块响应于第一控制信号而导通上拉模块。第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

7. 发明申请

US20120051494A1 SHIFT REGISTER CIRCUIT 有权
标题翻译：移位寄存器电路
公开(公告)号：US20120051494A1
公开(公告)日：2012-03-01
申请号：US13044773
申请日：2011-03-10
申请人： Yu-Chung YANG , Yung-Chih CHEN , Chih-Ying LIN , Kun-Yueh LIN
发明人： Yu-Chung YANG , Yung-Chih CHEN , Chih-Ying LIN , Kun-Yueh LIN
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3674 , G09G3/3685 , G09G2300/0417 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
摘要： A shift register circuit includes a plurality of shift registers. Each of the shift registers is configured for outputting a corresponding start-pulse signal and a corresponding driving-pulse signal. Each of the shift registers includes a pull-up circuit, a first driving circuit, a second driving circuit and a discharging circuit. The pull-up circuit is configured for charging a first node. The first driving circuit is configured for generating the corresponding start-pulse signal, and the second driving circuit is configured for generating the corresponding driving-pulse signal. The discharging circuit firstly discharges the first node before discharging an output terminal of the second driving circuit.
摘要翻译：移位寄存器电路包括多个移位寄存器。每个移位寄存器被配置为输出相应的起始脉冲信号和相应的驱动脉冲信号。每个移位寄存器包括上拉电路，第一驱动电路，第二驱动电路和放电电路。上拉电路被配置为对第一节点进行充电。第一驱动电路被配置为产生相应的起始脉冲信号，并且第二驱动电路被配置为产生相应的驱动脉冲信号。在放电第二驱动电路的输出端子之前，放电电路首先对第一节点进行放电。

8. 发明授权

US08049828B2 Flat-panel display device having test architecture 有权
标题翻译：具有测试架构的平板显示设备
公开(公告)号：US08049828B2
公开(公告)日：2011-11-01
申请号：US12178662
申请日：2008-07-24
申请人： Chun-Hsin Liu , Yung-Chih Chen , Po-Yuan Liu , Tsung-Ting Tsai
发明人： Chun-Hsin Liu , Yung-Chih Chen , Po-Yuan Liu , Tsung-Ting Tsai
IPC分类号： G02F1/1333 , G02F1/1345
CPC分类号： G02F1/1362 , G02F1/13454 , G02F1/136286 , G02F2001/136254 , G02F2203/69
摘要： A flat-panel display device having test architecture is disclosed for disposing shorting bars without sacrificing wiring-on-array bus layout area of the outer-lead-bonding region. The flat-panel display device essentially includes a substrate having a plurality of driving integrated-circuit (IC) mounting areas, a plurality of signal lines and transmission lines disposed on the substrate, and a plurality of shorting bars disposed on the driving IC mounting areas. Each shorting bar is coupled to a corresponding signal line and a corresponding transmission line. Furthermore, in order to take out the laser-cutting process in the fabrication of the flat-panel display device for saving production cost, each driving IC mounting area is further disposed with a plurality of transistors for controlling the signal connections between the shorting bars and the signal lines, and also for controlling the signal connections between the shorting bars and the transmission lines.
摘要翻译：公开了一种具有测试架构的平板显示装置，用于在不牺牲外引线接合区域的阵列总线布局面积的情况下设置短路棒。平板显示装置基本上包括具有多个驱动集成电路（IC）安装区域的基板，设置在基板上的多条信号线和传输线以及设置在驱动IC安装区域上的多个短路棒。每个短路条耦合到对应的信号线和对应的传输线。此外，为了在制造平板显示装置的同时取出激光切割工艺以节省生产成本，每个驱动IC安装区域还配置有多个晶体管，用于控制短路棒和短路棒之间的信号连接信号线，并且还用于控制短路棒和传输线之间的信号连接。

9. 发明申请

US20110234577A1 SHIFT REGISTER WITH LOW POWER CONSUMPTION 有权
标题翻译：具有低功耗的移位寄存器
公开(公告)号：US20110234577A1
公开(公告)日：2011-09-29
申请号：US12730576
申请日：2010-03-24
申请人： Yu-Chung Yang , Yung-Chih Chen , Chih-Ying Lin , Kuo-Hua Hsu
发明人： Yu-Chung Yang , Yung-Chih Chen , Chih-Ying Lin , Kuo-Hua Hsu
IPC分类号： G06F3/038 , G11C19/00
CPC分类号： G11C19/28 , G09G3/3677 , G09G2300/0408
摘要： A shift register comprises a plurality of stages. In one embodiment, each stage includes a first output, a second output, a pull-up circuit electrically coupled between a node and the second output, a pull-up control circuit electrically coupled to the node, a pull-down control circuit electrically coupled between the node and the first output, and a control circuit electrically coupled to the node and the first output.
摘要翻译：移位寄存器包括多个级。在一个实施例中，每个级包括第一输出，第二输出，电耦合在节点和第二输出之间的上拉电路，电耦合到该节点的上拉控制电路，电耦合的下拉控制电路在所述节点和所述第一输出之间，以及控制电路，电连接到所述节点和所述第一输出。

10. 发明授权

US08027426B1 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08027426B1
公开(公告)日：2011-09-27
申请号：US12837244
申请日：2010-07-15
申请人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G2310/0286 , G11C19/184
摘要： An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.
摘要翻译：示例性移位寄存器包括多个晶体管。对晶体管进行起始脉冲信号，第一时钟信号和第二时钟信号的控制，以产生栅极驱动信号。第一时钟信号和第二时钟信号相对于彼此相位反相。第一时钟信号的逻辑低电平和第二时钟信号的另一个逻辑低电平彼此不同。而且，晶体管是负阈值电压晶体管。在晶体管处于截止状态的情况下，每个晶体管的栅极处的电位低于晶体管的源极/漏极处的另一个电位。

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