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1. 发明授权

US08719755B2 Graded dummy insertion 有权
标题翻译：分级虚拟插入
公开(公告)号：US08719755B2
公开(公告)日：2014-05-06
申请号：US13562638
申请日：2012-07-31
申请人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
发明人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.
摘要翻译：除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。例如，第一图案密度和第二图案密度是门密度和/或多密度。为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。

2. 发明申请

US20140042585A1 SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM 有权
标题翻译：用于设计半导体器件的系统，器件制造和使用该系统的方法
公开(公告)号：US20140042585A1
公开(公告)日：2014-02-13
申请号：US13569717
申请日：2012-08-08
申请人： Yung-Chow PENG , Wen-Shen CHOU , Jaw-Juinn HORNG
发明人： Yung-Chow PENG , Wen-Shen CHOU , Jaw-Juinn HORNG
IPC分类号： G06F17/50 , H01L27/00
CPC分类号： H01L27/0207 , G06F17/5072 , G06F17/5081
摘要： This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.
摘要翻译：本公开涉及制造半导体器件的方法。该方法包括将半导体器件的示意图设计与半导体器件的布局设计进行比较。该方法还包括基于布局设计生成布局样式信息，并基于布局设计和原理图设计生成阵列边缘信息。该方法还包括使用布局样式信息和阵列边缘信息来选择性地修改使用智能虚拟插入的布局设计。该方法还包括使用布局样式信息和阵列边缘信息对修改的布局设计执行设计规则检查。本公开还涉及一种用于制造半导体器件和半导体器件的系统。

3. 发明申请

US20130185689A1 METHOD OF AND SYSTEM FOR GENERATING OPTIMIZED SEMICONDUCTOR COMPONENT LAYOUT 有权
标题翻译：用于生成优化的半导体元件布局的方法和系统
公开(公告)号：US20130185689A1
公开(公告)日：2013-07-18
申请号：US13352738
申请日：2012-01-18
申请人： Chien-Hung CHEN , Yung-Chow PENG , Chung-Hui CHEN , Chih Ming YANG
发明人： Chien-Hung CHEN , Yung-Chow PENG , Chung-Hui CHEN , Chih Ming YANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/12 , H01L27/0207 , H01L29/94
摘要： A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.
摘要翻译：根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部。对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

4. 发明授权

US08378742B2 Driver for a semiconductor chip 有权
标题翻译：驱动器用于半导体芯片
公开(公告)号：US08378742B2
公开(公告)日：2013-02-19
申请号：US12987464
申请日：2011-01-10
申请人： Renjeng Chiang , Yung-Chow Peng
发明人： Renjeng Chiang , Yung-Chow Peng
IPC分类号： H01L25/00
CPC分类号： H01L27/0207 , H01L23/4824 , H01L23/5286 , H01L23/5329 , H01L24/05 , H01L27/092 , H01L2224/04042 , H01L2224/05014 , H01L2924/01068 , H01L2924/10253 , H01L2924/13091 , H01L2924/00
摘要： A driver for a semiconductor chip, the driver having a drain wire with a first end and a second end and p and n-type transistors each with a source, gate and drain. The source of the p-type transistors connected to a positive power supply line, the source of the n-type transistors connected to a ground power supply line. The gates of the p and n-type transistors connected to a first and second input signals respectively. The drains of the p and n-type transistors connected to the drain wire. The p and n-type transistors arranged so that a difference between a number of n-type transistors connected to the drain wire and a number of p-type transistors connected to the drain wire between the first end of the drain wire and all distances along the drain wire being less than two.
摘要翻译：一种用于半导体芯片的驱动器，该驱动器具有带有第一端和第二端的漏极线以及分别具有源极，栅极和漏极的p型和n型晶体管。连接到正电源线的p型晶体管的源极，连接到地电源线的n型晶体管的源极。分别连接到第一和第二输入信号的p型和n型晶体管的栅极。连接到漏极线的p型和n型晶体管的漏极。 p型和n型晶体管被布置成使得连接到漏极线的n个晶体管的数量与在漏极线的第一端之间连接到漏极线的多个p型晶体管之间的差异与所有距离漏极线小于2。

5. 发明申请

US20120262209A1 Multi-Phase Clock Generator and Data Transmission Lines 有权
标题翻译：多相时钟发生器和数据传输线
公开(公告)号：US20120262209A1
公开(公告)日：2012-10-18
申请号：US13089160
申请日：2011-04-18
申请人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03K5/15066 , H03K5/133 , H03K2005/00058 , H03L7/06
摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.
摘要翻译：实施例是集成电路。集成电路包括时钟发生器和数据传输线。时钟发生器产生时钟信号。至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。至少部分地通过至少一个时钟信号来触发每个数据传输线。

6. 发明申请

US20110260746A1 BUILT-IN SELF-TEST CIRCUIT FOR LIQUID CRYSTAL DISPLAY SOURCE DRIVER 有权
标题翻译：用于液晶显示源驱动器的内置自检电路
公开(公告)号：US20110260746A1
公开(公告)日：2011-10-27
申请号：US12764346
申请日：2010-04-21
申请人： Jui-Cheng HUANG , Yung-Chow PENG , Ruey-Bin SHEEN
发明人： Jui-Cheng HUANG , Yung-Chow PENG , Ruey-Bin SHEEN
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G09G3/3685 , G09G3/006 , G09G2310/027 , G09G2310/0291 , G09G2330/12
摘要： A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.
摘要翻译：用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置作为比较。第一输入信号和第二输入信号耦合到比较器。第一输入信号是预定的参考电压电平。第二输入信号是测试范围内的测试偏移电压。

7. 发明申请

US20110102086A1 INPUT COMMON MODE CIRCUIT 有权
标题翻译：输入公共模式电路
公开(公告)号：US20110102086A1
公开(公告)日：2011-05-05
申请号：US12917652
申请日：2010-11-02
申请人： Yu-Wei LIN , Yung-Chow PENG
发明人： Yu-Wei LIN , Yung-Chow PENG
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45475 , H03F3/45632 , H03F3/45928 , H03F2203/45512 , H03F2203/45588
摘要： A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level.
摘要翻译：电路提供对应于差分输入Inn和Inp的第一电流，以及对应于共模输入Vcm的第二电流。电路然后将差分电流和共模电流反射到第三电流和第四电流。基于镜像差分电流和镜像共模电流之间的差异，电路拉起或拉下这些电流，以平衡差分输入和共模输入之间的相应差值。实际上，该电路将输入共模电压调整到期望的电平，而不给它提供上升到不需要的电平的机会。

8. 发明申请

US20110057826A1 MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS), SYSTEMS, AND OPERATING METHODS THEREOF 有权
标题翻译：微电子机械系统（MEMS），系统及其操作方法
公开(公告)号：US20110057826A1
公开(公告)日：2011-03-10
申请号：US12856993
申请日：2010-08-16
申请人： Yung-Chow PENG , Wen-Hung HUANG , Yu-Wei LIN
发明人： Yung-Chow PENG , Wen-Hung HUANG , Yu-Wei LIN
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , B81B7/008 , H03M1/0626 , H03M1/12 , H03M3/30
摘要： A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that is capable of generating a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The MEMS is free from including any amplifier between the micro-mechanical structure and the ADC.
摘要翻译：微电子机械系统（MEMS）包括能够产生第一电信号的微机械结构。模数转换器（ADC）与微机械结构耦合。 MEMS不包括微机械结构和ADC之间的任何放大器。

9. 发明授权

US06593775B2 Insulatior for a multi-power system 失效
公开(公告)号：US06593775B2
公开(公告)日：2003-07-15
申请号：US09761930
申请日：2001-01-17
申请人： Kou-Hwa Yu , Jui-Chiang Wang , Yung-Chow Peng
发明人： Kou-Hwa Yu , Jui-Chiang Wang , Yung-Chow Peng
IPC分类号： H03K19185
CPC分类号： G06F1/32 , G06F1/26
摘要： This invention relates to an insulator for a multi-power system, which is used to resolve the current leakage which comes from each power supplied to the corresponding devices which are not being correctly operated. The isolating device includes: a first power supply for providing an operating power to the isolating device; a level detector for detecting the voltage level of the operating power; a signal isolation controller for changing the output level of the circuit supplied by the operating power based on the operating power detected; and a second power for supplying a real-time power to circuit for power saving operation based on the changed output level.

10. 发明授权

US06473282B1 Latch-up protection circuit for integrated circuits biased with multiple power supplies and its method 失效
标题翻译：用于多电源偏置的集成电路的锁存保护电路及其方法
公开(公告)号：US06473282B1
公开(公告)日：2002-10-29
申请号：US09547186
申请日：2000-04-11
申请人： Shi-Tron Lin , Ta-Lee Yu , Yung-Chow Peng
发明人： Shi-Tron Lin , Ta-Lee Yu , Yung-Chow Peng
IPC分类号： H02H320
CPC分类号： H01L27/0251
摘要： A latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail is disclosed, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.
摘要翻译：公开了一种用于通过第一电力轨道和第二电力轨道供电的集成电路的闩锁保护电路，该集成电路具有至少一个导电类型的半导体本体。闩锁保护电路包括控制电路和开关电路。控制电路连接到第一电源轨和第二电源轨，用于检测它们之间的相对电压，并产生第一控制信号和第二控制信号。开关电路连接到第一电源轨和控制电路。当相对电压大于第一预定值时，响应于第一控制信号的开关电路将第一电源轨与至少一个半导体块电连接。当相对电压小于第一预定值时，响应于第一控制信号的开关将第一电力轨与至少一个半导体块电气断开。

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