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1. 发明授权

US09059034B2 EEPROM 有权
公开(公告)号：US09059034B2
公开(公告)日：2015-06-16
申请号：US13216367
申请日：2011-08-24
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： H01L27/115 , H01L29/788 , G11C16/04 , G11C16/10 , H01L29/66
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/10 , H01L27/11524 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要： An EEPROM includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. First through fifth impurity regions are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, and first and second floating gates are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, first and second tunnel windows are respectively formed at portions in contact with the first and second floating gates. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in the top layer portion of the semiconductor layer that opposes the second tunnel window.
摘要翻译：一种EEPROM包括：第一导电类型的半导体层; 以及形成在所述半导体层上的第一绝缘膜。在半导体层的顶层部分中形成第一至第五杂质区。在第一绝缘膜上，选择栅极和第一和第二浮置栅极分别设置在第一杂质区域和第二杂质区域之间的区域，第二杂质区域和第三杂质区域之间的区域以及第二杂质区域之间的区域第三杂质区和第四杂质区。在第一绝缘膜中，第一和第二隧道窗分别形成在与第一和第二浮动栅极接触的部分处。在与第二隧道窗口相对的半导体层的顶层部分中形成连接到第二杂质区的第二导电类型的第六杂质区。

2. 发明授权

US08089116B2 FLOTOX-TYPE EEPROM and method for manufacturing the same 有权
标题翻译： FLOTOX型EEPROM及其制造方法
公开(公告)号：US08089116B2
公开(公告)日：2012-01-03
申请号：US12596216
申请日：2008-04-16
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A FLOTOX-TYPE EEPROM of the invention has a configuration wherein an N region 25 as an impurity region formed under a tunnel window 12 and a channel stopper region 19 formed under a LOCOS oxide film 18 are spaced apart by a predetermined distance Y. Therefore, the tunnel window 12 does not sustain damage if an excessive voltage is applied to the tunnel window 12. As a result, the FLOTOX-TYPE EEPROM is adapted to limit the voltage applied to the tunnel window 12 and to reduce stress on the tunnel window 12 and can achieve an increased number of rewrites.
摘要翻译：本发明的FLOTOX型EEPROM具有这样的结构，其中形成在隧道窗12下方的杂质区域N区25和形成在LOCOS氧化物膜18下方的通道阻挡区域19间隔开预定距离Y.因此，如果向隧道窗口12施加过大的电压，则隧道窗口12不会受到损坏。结果，FLOTOX型EEPROM适于限制施加到隧道窗口12的电压并且减小隧道窗口12上的应力并可以实现更多的重写。

3. 发明授权

US07579633B2 Photoelectric conversion device, image sensor, and method for manufacturing photoelectric conversion device 有权
标题翻译：光电转换装置，图像传感器以及光电转换装置的制造方法
公开(公告)号：US07579633B2
公开(公告)日：2009-08-25
申请号：US10566667
申请日：2005-05-02
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： H01L27/15
CPC分类号： H01L27/14645 , H01L27/1463
摘要： A photoelectric conversion device includes a photoelectric conversion layer that is stacked on a semiconductor substrate and that has first, second, and third photoelectric conversion regions, and first, second, and third dividing regions. The first dividing region is formed at a predetermined depth from a surface of the photoelectric conversion layer in the first photoelectric conversion region, and divides the first photoelectric conversion region into a first surface side region closer to the surface thereof and a first substrate side region closer to the semiconductor substrate. The first dividing region has a through hole. The second dividing region is formed at substantially the same depth as the first dividing region or at a shallower depth than the first dividing region in the second photoelectric conversion region. The third dividing region is formed at a shallower depth than the second dividing region in the third photoelectric conversion region.
摘要翻译：光电转换装置包括堆叠在半导体基板上并具有第一，第二和第三光电转换区域以及第一，第二和第三分割区域的光电转换层。第一分割区域形成在距第一光电转换区域中的光电转换层的表面的预定深度处，并且将第一光电转换区域分割成更靠近其表面的第一表面侧区域和靠近第一光电转换区域的第一基板侧区域到半导体衬底。第一分割区域具有通孔。第二分割区域形成为与第一分割区域大致相同的深度，或者形成在比第二光电转换区域中的第一分割区域浅的深度。第三分割区域形成在比第三光电转换区域中的第二分割区域浅的深度处。

4. 发明申请

US20100002524A1 FLOTOX-TYPE EEPROM 有权
标题翻译： FLOTOX型EEPROM
公开(公告)号：US20100002524A1
公开(公告)日：2010-01-07
申请号：US12449169
申请日：2008-01-28
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： G11C16/04
CPC分类号： H01L29/7883 , G11C16/0433 , G11C16/10 , G11C16/3436 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42328 , H01L29/66825
摘要： In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates (25a, 25b), two tunnel windows (33a, 33b) a shared source (27), a shared control gate (26), select gates (29a, 29b), and a shared drain 28. Thus, a higher reliability design and a higher breakdown voltage design are achieved for the FLOTOX EEPROM of the dual cell type.
摘要翻译：在设计双电池类型的FLOTOX EEPROM时，应考虑用于FLOTOX EEPROM微型化的电池的布局。双电池类型的FLOTOX EEPROM包括两个成对的浮动栅极（25a，25b），两个隧道窗口（33a，33b），共享源（27），共享控制栅极（26），选择栅极（29a，29b）和共用漏极28.因此，对于双电池型的FLOTOX EEPROM，实现了更高的可靠性设计和更高的击穿电压设计。

5. 发明申请

US20100084699A1 FLOTOX-TYPE EEPROM AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： FLOTOX型EEPROM及其制造方法
公开(公告)号：US20100084699A1
公开(公告)日：2010-04-08
申请号：US12596216
申请日：2008-04-16
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： H01L29/788 , H01L21/26
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A FLOTOX-TYPE EEPROM of the invention has a configuration wherein an N region 25 as an impurity region formed under a tunnel window 12 and a channel stopper region 19 formed under a LOCOS oxide film 18 are spaced apart by a predetermined distance Y. Therefore, the tunnel window 12 does not sustain damage if an excessive voltage is applied to the tunnel window 12. As a result, the FLOTOX-TYPE EEPROM is adapted to limit the voltage applied to the tunnel window 12 and to reduce stress on the tunnel window 12 and can achieve an increased number of rewrites.
摘要翻译：本发明的FLOTOX型EEPROM具有这样的结构，其中形成在隧道窗12下方的杂质区域N区25和形成在LOCOS氧化物膜18下方的通道阻挡区域19间隔开预定距离Y.因此，如果向隧道窗口12施加过大的电压，则隧道窗口12不会受到损坏。结果，FLOTOX型EEPROM适于限制施加到隧道窗口12的电压并且减小隧道窗口12上的应力并可以实现更多的重写。

6. 发明授权

US07411265B2 Photodiode and phototransistor 有权
标题翻译：光电二极管和光电晶体管
公开(公告)号：US07411265B2
公开(公告)日：2008-08-12
申请号：US11463347
申请日：2006-08-09
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： H01L31/06
CPC分类号： H01L31/109 , H01L31/035281 , Y02E10/50
摘要： A phototransistor includes a first-conduction-type lower region, a second-conduction-type upper region disposed on the first region, a second-conduction-type electrode contact region of a high concentration disposed at a surface inside of the upper region and is connected to an electrode so as to transmit a signal, a first-conduction-type first shield region of a high concentration disposed at the surface of the upper region and spaced at an interval from the electrode contact region and connected to a ground potential, and a first-conduction-type second shield region of a low concentration disposed between the electrode contact region and the first shield region at the surface of the upper region so as to surround the electrode contact region, and further, is connected to the ground potential.
摘要翻译：光电晶体管包括第一导电型下部区域，设置在第一区域上的第二导电型上部区域，设置在上部区域的内表面的高浓度的第二导电型电极接触区域，并且是连接到电极以便传输信号，高浓度的第一导电型第一屏蔽区域设置在上部区域的表面并与电极接触区域间隔开并连接到接地电位，以及低浓度的第一导电型第二屏蔽区域设置在电极接触区域和上部区域的表面处的第一屏蔽区域之间，以便包围电极接触区域，并且还连接到接地电位。

7. 发明授权

US08072807B2 FLOTOX type EEPROM 有权
标题翻译： FLOTOX型EEPROM
公开(公告)号：US08072807B2
公开(公告)日：2011-12-06
申请号：US12594751
申请日：2008-04-02
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0408 , H01L27/11524 , H01L29/7883
摘要： A FLOTOX EEPROM of the invention includes: a plurality of floating gates 11 arranged in array, each having a tunnel window 12 and allowing electron injection and extraction via the tunnel window; a plurality of select gates 13 provided in one-on-one correspondence to the plural floating gates 11; a control gate 16 shared by the plural floating gates 11; a source 17 shared by the plural floating gates 11; and a drain 18 shared by the plural floating gates 11. Therefore, the FLOTOX EEPROM does not encounter the decrease of junction breakdown voltage of a drain region, allowing the application of sufficiently high write voltage. Further, cell area can be reduced.
摘要翻译：本发明的FLOTOX EEPROM包括：排列成阵列的多个浮动栅极11，每个具有隧道窗口12，并允许通过隧道窗口进行电子注入和提取; 与多个浮动栅极11一一对应地设置的多个选择栅极13; 由多个浮动门11共享的控制栅极16; 由多个浮动门11共享的源极17; 以及由多个浮置栅极11共享的漏极18，因此，FLOTOX EEPROM不会遇到漏极区域的结击穿电压的降低，从而允许施加足够高的写入电压。此外，可以减少单元面积。

8. 发明授权

US08050105B2 FLOTOX-type EEPROM 有权
标题翻译： FLOTOX型EEPROM
公开(公告)号：US08050105B2
公开(公告)日：2011-11-01
申请号：US12449169
申请日：2008-01-28
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： G11C11/34
CPC分类号： H01L29/7883 , G11C16/0433 , G11C16/10 , G11C16/3436 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42328 , H01L29/66825
摘要： In designing a FLOTOX EEPROM of a dual cell type, a consideration should be given to the layout of cells for microminiaturization of the FLOTOX EEPROM. The FLOTOX EEPROM of the dual cell type includes two paired floating gates (25a, 25b), two tunnel windows (33a, 33b) a shared source (27), a shared control gate (26), select gates (29a, 29b), and a shared drain 28. Thus, a higher reliability design and a higher breakdown voltage design are achieved for the FLOTOX EEPROM of the dual cell type.
摘要翻译：在设计双电池类型的FLOTOX EEPROM时，应考虑用于FLOTOX EEPROM微型化的电池的布局。双电池类型的FLOTOX EEPROM包括两个成对的浮动栅极（25a，25b），两个隧道窗口（33a，33b），共享源（27），共享控制栅极（26），选择栅极（29a，29b）和共用漏极28.因此，对于双电池型的FLOTOX EEPROM，实现了更高的可靠性设计和更高的击穿电压设计。

9. 发明授权

US07556980B2 Photodiode and phototransistor 有权
标题翻译：光电二极管和光电晶体管
公开(公告)号：US07556980B2
公开(公告)日：2009-07-07
申请号：US12060968
申请日：2008-04-02
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： H01L21/00
CPC分类号： H01L31/109 , H01L31/035281 , Y02E10/50
摘要： A phototransistor includes a first-conduction-type lower region, a second-conduction-type upper region disposed on the first region, a second-conduction-type electrode contact region of a high concentration disposed at a surface inside of the upper region and is connected to an electrode so as to transmit a signal, a first-conduction-type first shield region of a high concentration disposed at the surface of the upper region and spaced at an interval from the electrode contact region and connected to a ground potential, and a first-conduction-type second shield region of a low concentration disposed between the electrode contact region and the first shield region at the surface of the upper region so as to surround the electrode contact region, and further, is connected to the ground potential.
摘要翻译：光电晶体管包括第一导电型下部区域，设置在第一区域上的第二导电型上部区域，设置在上部区域的内表面的高浓度的第二导电型电极接触区域，并且是连接到电极以便传输信号，高浓度的第一导电型第一屏蔽区域设置在上部区域的表面并与电极接触区域间隔开并连接到接地电位，以及低浓度的第一导电型第二屏蔽区域设置在电极接触区域和上部区域的表面处的第一屏蔽区域之间，以便包围电极接触区域，并且还连接到接地电位。

10. 发明申请

US20120001251A1 EEPROM 有权
公开(公告)号：US20120001251A1
公开(公告)日：2012-01-05
申请号：US13216367
申请日：2011-08-24
申请人： Yushi Sekiguchi
发明人： Yushi Sekiguchi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/10 , H01L27/11524 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要： An EEPROM includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. First through fifth impurity regions are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, and first and second floating gates are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, first and second tunnel windows are respectively formed at portions in contact with the first and second floating gates. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in the top layer portion of the semiconductor layer that opposes the second tunnel window.
摘要翻译：一种EEPROM包括：第一导电类型的半导体层; 以及形成在所述半导体层上的第一绝缘膜。在半导体层的顶层部分中形成第一至第五杂质区。在第一绝缘膜上，选择栅极和第一和第二浮置栅极分别设置在第一杂质区域和第二杂质区域之间的区域，第二杂质区域和第三杂质区域之间的区域以及第二杂质区域之间的区域第三杂质区和第四杂质区。在第一绝缘膜中，第一和第二隧道窗分别形成在与第一和第二浮动栅极接触的部分处。在与第二隧道窗口相对的半导体层的顶层部分中形成连接到第二杂质区的第二导电类型的第六杂质区。

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