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    • 3. 发明申请
    • LINEAR IMAGE SENSOR IN CMOS TECHNOLOGY
    • CMOS技术中的线性图像传感器
    • US20110298956A1
    • 2011-12-08
    • US13152333
    • 2011-06-03
    • Benoit GIFFARDYvon CAZAUX
    • Benoit GIFFARDYvon CAZAUX
    • H04N5/335
    • H04N3/1525H01L27/14603H01L27/14609H01L27/14643H04N3/155H04N5/37206H04N5/3743
    • A time-delay-integration image sensor comprises a matrix of pixels organized in rows and columns. Each pixel comprises a first photosensitive element, a storage node and a first transfer element connected between the first photosensitive element and the storage node, Each pixel further comprises a second photosensitive element, a second transfer element connected between the second photosensitive element and the storage node, and a third transfer element connected between the storage node and the second photosensitive element of an adjacent pixel of the column. A control circuit is configured to simultaneously command the first and second transfer elements to on state and the third transfer element to off state, and, in a distinct phase, to simultaneously command the first and third transfer elements to on state and the second transfer element to off state.
    • 时间延迟积分图像传感器包括以行和列组织的像素矩阵。 每个像素包括第一感光元件,存储节点和连接在第一感光元件和存储节点之间的第一传输元件。每个像素还包括第二感光元件,连接在第二感光元件和存储节点之间的第二传输元件 以及连接在该列的相邻像素的存储节点和第二感光元件之间的第三传送元件。 控制电路被配置为同时将第一和第二传递元件命令为导通状态,并将第三传递元件命令为断开状态,并且在不同的相位中,同时将第一和第三传递元件命令为接通状态,并且第二传递元件 关闭状态。
    • 8. 发明授权
    • Linear image sensor in CMOS technology
    • CMOS技术中的线性图像传感器
    • US08817150B2
    • 2014-08-26
    • US13152333
    • 2011-06-03
    • Benoit GiffardYvon Cazaux
    • Benoit GiffardYvon Cazaux
    • H04N3/14H04N5/335H04N5/374H01L27/146H04N5/372
    • H04N3/1525H01L27/14603H01L27/14609H01L27/14643H04N3/155H04N5/37206H04N5/3743
    • A time-delay-integration image sensor comprises a matrix of pixels organized in rows and columns. Each pixel comprises a first photosensitive element, a storage node and a first transfer element connected between the first photosensitive element and the storage node, Each pixel further comprises a second photosensitive element, a second transfer element connected between the second photosensitive element and the storage node, and a third transfer element connected between the storage node and the second photosensitive element of an adjacent pixel of the column. A control circuit is configured to simultaneously command the first and second transfer elements to on state and the third transfer element to off state, and, in a distinct phase, to simultaneously command the first and third transfer elements to on state and the second transfer element to off state.
    • 时间延迟积分图像传感器包括以行和列组织的像素矩阵。 每个像素包括第一感光元件,存储节点和连接在第一感光元件和存储节点之间的第一传输元件。每个像素还包括第二感光元件,连接在第二感光元件和存储节点之间的第二传输元件 以及连接在该列的相邻像素的存储节点和第二感光元件之间的第三传送元件。 控制电路被配置为同时将第一和第二传递元件命令为导通状态,并将第三传递元件命令为断开状态,并且在不同的相位中,同时将第一和第三传递元件命令为接通状态,并且第二传递元件 关闭状态。
    • 10. 发明授权
    • TDI image sensor in CMOS technology with high video capture rate
    • TDI图像传感器采用CMOS技术,视频采集率高
    • US08451354B2
    • 2013-05-28
    • US13103492
    • 2011-05-09
    • Yvon CazauxBenoit Giffard
    • Yvon CazauxBenoit Giffard
    • H04N3/14H04N5/335
    • H04N5/3743
    • An time-delay-integration image sensor comprises a matrix of photosensitive pixels organized in rows and columns, a first matrix of memory cells associated with control and adding means to store accumulated brightness levels of several rows of pixels in a row of memory cells. The first memory cell matrix is provided with the control and adding means to store in its rows accumulated brightness levels of the rows of a first half of the pixel matrix. The sensor comprises a second memory cell matrix associated with the control and adding means to store accumulated brightness levels of the rows of the second half of the pixel matrix in a row of the second memory cell matrix. Means are provided for adding the levels accumulated in a row of the first memory cell matrix to the levels accumulated in a corresponding row of the second memory cell matrix.
    • 时间延迟积分图像传感器包括以行和列组织的感光像素的矩阵,与控制相关联的存储器单元的第一矩阵和用于存储存储器单元行中的几行像素的累积亮度级别的附加装置。 第一存储单元矩阵设置有控制和加法装置,用于在其行中存储像素矩阵的前半部分的行的累积亮度级。 所述传感器包括与所述控制相关联的第二存储单元阵列和用于将所述像素矩阵的后半部分的行的累积亮度级别存储在所述第二存储单元矩阵的行中的相加装置。 提供了用于将第一存储单元矩阵的一行中累积的电平加到累积在第二存储单元矩阵的对应行中的电平的装置。