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1. 发明申请

US20170093007A1 Low Loss and Low Cross Talk Transmission Lines using Shaped Vias 有权
公开(公告)号：US20170093007A1
公开(公告)日：2017-03-30
申请号：US14866693
申请日：2015-09-25
申请人： Adel A. ELSHERBINI , Mathew Manusharow , Krishna Bharath , Zhichao Zhang , Yidnekachew S. Mekonnen , Aleksandar Aleksov , Henning Braunisch , Feras Eid , Javier Soto
发明人： Adel A. ELSHERBINI , Mathew Manusharow , Krishna Bharath , Zhichao Zhang , Yidnekachew S. Mekonnen , Aleksandar Aleksov , Henning Braunisch , Feras Eid , Javier Soto
IPC分类号： H01P3/08
CPC分类号： H05K1/0245 , H01P3/02 , H01P3/026 , H01P3/08 , H01P3/085 , H01P3/088
摘要： Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

2. 发明授权

US09491881B2 Microelectronic socket comprising a substrate and an insulative insert mated with openings in the substrate 有权
标题翻译：微电子插座，其包括衬底和与衬底中的开口配合的绝缘插入件
公开(公告)号：US09491881B2
公开(公告)日：2016-11-08
申请号：US14164403
申请日：2014-01-27
申请人： Joshua D. Heppner , Zhichao Zhang , Srikant Nekkanty , Michael Garcia
发明人： Joshua D. Heppner , Zhichao Zhang , Srikant Nekkanty , Michael Garcia
IPC分类号： H05K7/10 , H01R12/70 , H05K1/18 , H05K3/42
CPC分类号： H05K7/1069 , H01R12/7076 , H01R12/7082 , H05K1/184 , H05K3/42 , H05K2201/09545 , H05K2201/10189 , H05K2201/10265 , Y10T29/49222
摘要： A microelectronic socket having a two piece construction, wherein a first piece comprises a conductive socket substrate and the second piece comprises an insulative insert. The conductive socket substrate has a first surface, a second surface, and at least one opening extending therebetween. The insulative insert has a base portion with at least one projection extending therefrom. The insulative insert is mated with the conductive socket substrate such that the at least one projection resides within a corresponding conductive socket substrate opening. The insulative insert further includes a plurality of vias, wherein at least one of the plurality of vias extends through the insulative base and through an insulative insert projection, wherein a contact may be disposed within the via.
摘要翻译：一种具有两件式结构的微电子插座，其中第一件包括导电插座衬底，第二件包括绝缘插入件。导电插座基板具有第一表面，第二表面和在它们之间延伸的至少一个开口。绝缘插入件具有从其延伸的至少一个突起的基部。绝缘插入件与导电插座基板配合，使得至少一个突起位于相应的导电插座衬底开口内。绝缘插入件还包括多个通孔，其中多个通孔中的至少一个延伸穿过绝缘基底并穿过绝缘插入物突起，其中触点可以设置在通孔内。

3. 发明申请

US20160183374A1 CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES 有权
标题翻译： CPU封装基板与可拆卸的存储器机械接口
公开(公告)号：US20160183374A1
公开(公告)日：2016-06-23
申请号：US14575775
申请日：2014-12-18
申请人： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
发明人： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
IPC分类号： H05K1/18 , H01R12/72 , H05K1/11 , H05K1/02 , H05K3/30 , H05K3/34
CPC分类号： H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611
摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
摘要翻译：公开了可配置的中央处理单元（CPU）封装基板。描述了包括处理设备接口的封装衬底。封装衬底还包括设置在封装衬底上的存储器件电接口。封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。

4. 发明申请

US20140174808A1 REDUCED CAPACITANCE LAND PAD 审中-公开
标题翻译：减少电容土地垫
公开(公告)号：US20140174808A1
公开(公告)日：2014-06-26
申请号：US13727439
申请日：2012-12-26
申请人： Zhichao Zhang , Tao Wu , Gaurav Chawla , Jeffrey Lee
发明人： Zhichao Zhang , Tao Wu , Gaurav Chawla , Jeffrey Lee
IPC分类号： H05K1/11 , H05K13/00
CPC分类号： H05K1/113 , H05K1/0243 , H05K1/025 , H05K3/3452 , H05K2201/09663 , H05K2201/0969 , H05K2201/09881 , H05K2201/10719
摘要： A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.
摘要翻译：公开了一种具有减小的电容的平面栅格阵列（LGA）焊盘。通过衬垫的导电部分的厚度，通过一个或多个不导电的空隙来减小与衬底内的平行接地面重叠的焊盘的导电部分。空隙可以允许由焊盘的周边限定的焊盘的接触面积保持相同，同时减少与平行接地平面重叠的导电部分。焊盘和平行接地面之间的电容减少了与重叠导电面积减小成正比的量。

5. 发明申请

US20140162475A1 CONNECTOR ASSEMBLY AND METHOD 有权
标题翻译：连接器总成和方法
公开(公告)号：US20140162475A1
公开(公告)日：2014-06-12
申请号：US13711187
申请日：2012-12-11
申请人： Gaurav Chawla , Joshua D. Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
发明人： Gaurav Chawla , Joshua D. Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
IPC分类号： H01R12/71
CPC分类号： H01R12/722 , H01L23/34 , H01L2924/0002 , H01R12/7005 , H01R12/71 , H01R12/724 , H01R12/79 , H01R13/114 , H01L2924/00
摘要： Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
摘要翻译：显示连接器和耦合封装和管芯的方法。所选择的实例包括具有两个或更多台阶的插头和插座，其具有沿梯田提供的触点。连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。

6. 发明授权

US08643184B1 Crosstalk polarity reversal and cancellation through substrate material tuning 有权
标题翻译：串扰极性反转和消除通过基板材料调谐
公开(公告)号：US08643184B1
公开(公告)日：2014-02-04
申请号：US13665741
申请日：2012-10-31
申请人： Zhichao Zhang , Tolga Memioglu , Tao Wu , Kemal Aygun
发明人： Zhichao Zhang , Tolga Memioglu , Tao Wu , Kemal Aygun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/04
CPC分类号： H01L23/66 , H01L21/76877 , H01L23/49822 , H01L23/49838 , H01L23/50 , H01L23/5226 , H01L24/16 , H01L24/17 , H01L25/0655 , H01L25/18 , H01L2223/6627 , H01L2224/13023 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16237 , H01L2924/01029 , H01L2924/1426 , H01L2924/143 , H01L2924/14361 , H01L2924/15311 , H01L2924/3011 , H01P3/081 , H05K1/0216 , H05K1/0222 , H05K1/0228 , H01L2924/014 , H01L2924/00014
摘要： Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).
摘要翻译：具有分离信号迹线的第一介电材料的传输线和将信号迹线与接地平面分开的第二介电材料。在实施例中，互电容相对于自电容被调谐，以相对于沿着诸如电感耦合部分的通道的长度的其它互连部分感应到的远端串扰的极性反转。在实施例中，用于单端通道的传输线包括在与微带线或带状线导体相同的布线平面内具有较高介电常数的材料，以及在导体和接地平面之间具有较低介电常数的材料，。在实施例中，用于差分对的传输线包括在与微带线或带状线导体相同的布线平面内具有较低介电常数的材料，以及在导体和接地平面之间具有较高介电常数的材料。

7. 发明授权

US08614333B2 Acenaphtho heterocyclic compound and application thereof 有权
标题翻译：苊烯杂环化合物及其应用
公开(公告)号：US08614333B2
公开(公告)日：2013-12-24
申请号：US13810901
申请日：2011-07-27
申请人： Zhichao Zhang , Guiye Wu
发明人： Zhichao Zhang , Guiye Wu
IPC分类号： C07D209/80 , C07D417/10
CPC分类号： C07D209/80 , C07D209/70 , C07D417/10
摘要： The present invention relates to acenaphtho heterocyclic compounds and their uses in manufacturing the BH3 mimetics as Bcl-2-like protein inhibitors. Structures are shown in the following: Statistical analysis of their bio-activities showed these compounds exhibit better BH3 mimicking property than the reported compounds. These compounds can simulate BH3-only protein, competitively bind and antagonizing Bcl-2 and Mcl-1 proteins in vitro and in cells, and then induce apoptosis. Therefore, they all can be used in the manufactures of anticancer compounds.
摘要翻译：本发明涉及苊萘杂环化合物及其在制造BH3模拟物中作为Bcl-2样蛋白抑制剂的用途。结构如下所示：其生物活性的统计分析表明，这些化合物比所报道的化合物表现出更好的BH3模拟性质。这些化合物可以模拟BH3蛋白，在体外和细胞中竞争性地结合和拮抗Bcl-2和Mcl-1蛋白，然后诱导细胞凋亡。因此，它们都可用于抗癌化合物的制造。

8. 发明申请

US20120081858A1 FLEX CABLE AND METHOD FOR MAKING THE SAME 有权
标题翻译：柔性电缆及其制造方法
公开(公告)号：US20120081858A1
公开(公告)日：2012-04-05
申请号：US12896579
申请日：2010-10-01
申请人： Sanka Ganesan , Mohiuddin Mazumder , Zhichao Zhang , Kemal Aygun
发明人： Sanka Ganesan , Mohiuddin Mazumder , Zhichao Zhang , Kemal Aygun
IPC分类号： H05K7/00 , H01B5/00 , H05K1/00
CPC分类号： H05K7/00 , H05K1/181 , H05K3/28 , H05K3/282 , H05K3/361 , H05K2201/10356 , H05K2201/1053 , H05K2201/10734 , H05K2203/167 , Y02P70/611
摘要： An assembly of substrate packages interconnected with flex cables. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing detachable inter-package flex cable connection. The flex cable comprises a transmission region that includes a plurality of signal traces and a ground plane. A plurality of solder mask strips are disposed on the plurality of signals traces to provide anchoring for the signal traces. The solder mask strips intersect the signals traces. The exposed signal traces and the ground plane are coated with organic solderability preservative material. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.
摘要翻译：与柔性电缆互连的衬底封装的组件。该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。实施例涉及提供可拆卸的包装间柔性电缆连接的基板封装。柔性电缆包括包括多个信号迹线和接地平面的透射区域。多个焊接掩模条设置在多个信号迹线上以提供信号迹线的锚定。焊接掩模条与信号迹线相交。暴露的信号迹线和接地平面涂有有机可焊性防腐材料。在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

9. 发明授权

US09548734B1 Smart impedance matching for high-speed I/O 有权
标题翻译：智能阻抗匹配用于高速I / O
公开(公告)号：US09548734B1
公开(公告)日：2017-01-17
申请号：US14998090
申请日：2015-12-26
申请人： Hongjiang Song , Yan W. Song , Zhiguo Qian , Zhichao Zhang
发明人： Hongjiang Song , Yan W. Song , Zhiguo Qian , Zhichao Zhang
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0005 , H03K19/017545
摘要： Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.
摘要翻译：实施例通常涉及用于高速I / O的智能阻抗匹配。在一些实施例中，电路包括阻抗感测块; 有限状态机为驱动器提供阻抗调谐; 和控制块，控制块提供反馈回路来检查和调谐驱动器的阻抗。阻抗感测块用于对驱动器的输出电压进行采样，以确定驱动器的阻抗是否大于或小于通道的阻抗; 并且有限状态机基于确定驾驶员的阻抗是否大于或小于通道的阻抗来产生信号以减小或增加驾驶员的阻抗。

10. 发明申请

US20150214665A1 TWO PIECE SHIELDED SOCKET 有权
标题翻译：两件式屏蔽插座
公开(公告)号：US20150214665A1
公开(公告)日：2015-07-30
申请号：US14164403
申请日：2014-01-27
申请人： Joshua D. Heppner , Zhichao Zhang , Srikant Nekkanty , Michael Garcia
发明人： Joshua D. Heppner , Zhichao Zhang , Srikant Nekkanty , Michael Garcia
IPC分类号： H01R13/6461 , H01R43/18 , H01R12/71
CPC分类号： H05K7/1069 , H01R12/7076 , H01R12/7082 , H05K1/184 , H05K3/42 , H05K2201/09545 , H05K2201/10189 , H05K2201/10265 , Y10T29/49222
摘要： A microelectronic socket having a two piece construction, wherein a first piece comprises a conductive socket substrate and the second piece comprises an insulative insert. The conductive socket substrate has a first surface, a second surface, and at least one opening extending therebetween. The insulative insert has a base portion with at least one projection extending therefrom. The insulative insert is mated with the conductive socket substrate such that the at least one projection resides within a corresponding conductive socket substrate opening. The insulative insert further includes a plurality of vias, wherein at least one of the plurality of vias extends through the insulative base and through an insulative insert projection, wherein a contact may be disposed within the via.
摘要翻译：一种具有两件式结构的微电子插座，其中第一件包括导电插座衬底，第二件包括绝缘插入件。导电插座基板具有第一表面，第二表面和在它们之间延伸的至少一个开口。绝缘插入件具有从其延伸的至少一个突起的基部。绝缘插入件与导电插座基板配合，使得至少一个突起位于相应的导电插座衬底开口内。绝缘插入件还包括多个通孔，其中多个通孔中的至少一个延伸穿过绝缘基底并穿过绝缘插入物突起，其中触点可以设置在通孔内。

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