专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080291729A1 Non-Volatile Memory With High Reliability 有权
标题翻译：非易失性存储器具有高可靠性
公开(公告)号：US20080291729A1
公开(公告)日：2008-11-27
申请号：US12106777
申请日：2008-04-21
申请人： A. Peter Cosmin , Sorin S. Georgescu , George Smarandoiu , Adrian M. Tache
发明人： A. Peter Cosmin , Sorin S. Georgescu , George Smarandoiu , Adrian M. Tache
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.
摘要翻译：非易失性存储器（NVM）系统包括一组NVM单元，每个NVM单元包括：NVM晶体管; 将NVM晶体管耦合到对应的位线的存取晶体管; 以及将NVM晶体管耦合到公共源的源极选择晶体管。 NVM单元由包括擦除阶段和程序阶段的两相操作来写入。在擦除和编程阶段期间，将一组常见的位线电压施加到位线。接入晶体管导通，并且在擦除和编程阶段期间，源选择晶体管截止。在擦除阶段期间，将第一控制电压施加到NVM晶体管的控制栅极，并且在编程阶段期间将第二控制电压施加到NVM晶体管的控制栅极。在这些条件下，Fowler-Nordheim隧道掘进作业的平均要求数量减少了。

2. 发明授权

US07830714B2 Non-volatile memory with high reliability 有权
标题翻译：非易失性存储器具有高可靠性
公开(公告)号：US07830714B2
公开(公告)日：2010-11-09
申请号：US12106777
申请日：2008-04-21
申请人： A. Peter Cosmin , Sorin S. Georgescu , George Smarandoiu , Adrian M. Tache
发明人： A. Peter Cosmin , Sorin S. Georgescu , George Smarandoiu , Adrian M. Tache
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.
摘要翻译：非易失性存储器（NVM）系统包括一组NVM单元，每个NVM单元包括：NVM晶体管; 将NVM晶体管耦合到对应的位线的存取晶体管; 以及将NVM晶体管耦合到公共源的源极选择晶体管。 NVM单元由包括擦除阶段和程序阶段的两相操作来写入。在擦除和编程阶段期间，将一组常见的位线电压施加到位线。接入晶体管导通，并且在擦除和编程阶段期间，源选择晶体管截止。在擦除阶段期间，将第一控制电压施加到NVM晶体管的控制栅极，并且在编程阶段期间将第二控制电压施加到NVM晶体管的控制栅极。在这些条件下，Fowler-Nordheim隧道掘进作业的平均要求数量减少了。

3. 发明申请

US20120140565A1 Scalable Electrically Eraseable And Programmable Memory 有权
标题翻译：可扩展电擦除和可编程存储器
公开(公告)号：US20120140565A1
公开(公告)日：2012-06-07
申请号：US13365216
申请日：2012-02-02
申请人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
IPC分类号： G11C16/04
CPC分类号： G11C16/0458 , G11C16/0433 , H01L21/82385 , H01L21/823857 , H01L27/105 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/7881
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括连接到第一位线的第一非易失性存储器晶体管，连接到第二位线的第二非易失性存储晶体管和耦合到公共源极线的源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一扩散区域和与第二非易失性存储晶体管的源极区域连续的第二扩散区域。

4. 发明授权

US08750041B2 Scalable electrically erasable and programmable memory 有权
标题翻译：可扩展的电可擦除和可编程存储器
公开(公告)号：US08750041B2
公开(公告)日：2014-06-10
申请号：US13365216
申请日：2012-02-02
申请人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , A. Peter Cosmin , George Smarandoiu
IPC分类号： G11C16/04 , H01L29/788 , H01L27/115
CPC分类号： G11C16/0458 , G11C16/0433 , H01L21/82385 , H01L21/823857 , H01L27/105 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/42328 , H01L29/7881
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括连接到第一位线的第一非易失性存储器晶体管，连接到第二位线的第二非易失性存储晶体管和耦合到公共源极线的源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一扩散区域和与第二非易失性存储晶体管的源极区域连续的第二扩散区域。

5. 发明授权

US08139408B2 Scalable electrically eraseable and programmable memory 有权
标题翻译：可扩展的电可擦除和可编程存储器
公开(公告)号：US08139408B2
公开(公告)日：2012-03-20
申请号：US12050491
申请日：2008-03-18
申请人： Sorin S. Georgescu , Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , Peter Cosmin , George Smarandoiu
IPC分类号： G11C11/34
CPC分类号： G11C16/0458 , G11C16/0433 , H01L21/823857 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储晶体管，第二非易失性存储晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储晶体管的源极区域连续的第二源极区域和与位于与EEPROM单元对相同行的其它非易失性存储器晶体管的源极区域连续的第三源极区域。

6. 发明授权

US07528436B2 Scalable electrically eraseable and programmable memory 有权
标题翻译：可扩展的电可擦除和可编程存储器
公开(公告)号：US07528436B2
公开(公告)日：2009-05-05
申请号：US11470245
申请日：2006-09-05
申请人： Sorin S. Georgescu , Adam Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , Adam Peter Cosmin , George Smarandoiu
IPC分类号： H01L29/76
CPC分类号： G11C16/0433 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储晶体管，第二非易失性存储晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储晶体管的源极区域连续的第二源极区域和向下延伸穿过第一阱区域以接触第二阱区域的漏极区域。第一，第二和第三半导体区域和第二阱区域具有第一导电类型，并且第一阱区域具有与第一导电类型相反的第二导电类型。

7. 发明申请

US20080165582A1 Scalable Electrically Eraseable And Programmable Memory 有权
标题翻译：可扩展电擦除和可编程存储器
公开(公告)号：US20080165582A1
公开(公告)日：2008-07-10
申请号：US12050491
申请日：2008-03-18
申请人： Sorin S. Georgescu , Peter Cosmin , George Smarandoiu
发明人： Sorin S. Georgescu , Peter Cosmin , George Smarandoiu
IPC分类号： G06F17/50
CPC分类号： G11C16/0458 , G11C16/0433 , H01L21/823857 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
摘要翻译：包括一个或多个EEPROM单元对的非易失性存储器。每个EEPROM单元对包括三个晶体管，并存储两个数据位，有效地提供一个1.5晶体管EEPROM单元。 EEPROM单元对包括第一非易失性存储晶体管，第二非易失性存储晶体管和源极存取晶体管。源极存取晶体管包括：与第一非易失性存储晶体管的源极区域连续的第一源极区域; 与第二非易失性存储晶体管的源极区域连续的第二源极区域和与位于与EEPROM单元对相同行的其它非易失性存储器晶体管的源极区域连续的第三源极区域。

8. 发明授权

US5434815A Stress reduction for non-volatile memory cell 失效
标题翻译：非易失性记忆体的压力降低
公开(公告)号：US5434815A
公开(公告)日：1995-07-18
申请号：US184227
申请日：1994-01-19
申请人： George Smarandoiu , Steven J. Schumann , Tsung-Ching Wu
发明人： George Smarandoiu , Steven J. Schumann , Tsung-Ching Wu
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08
摘要： Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective for grounding the gate of a variable threshold programmable transistor in the memory cell. Power down of the word line is reflected in synchronous power-down of the sense line. Additionally, with power down, the sense amplifier for the particular core memory cell is disconnected from a master latch circuit, which in turn is connected to a slave latch circuit for applying the previous sense amplifier output to an input/output buffer, in order to secure the data sensed in core memory during read operation. The invention further permits reduced word line voltages during erase operation on the sense line and the variable threshold programmable transistor.
摘要翻译：非易失性半导体核心存储器性能通过减少核心存储器单元的应力来增强。在字线控制下，通过选择性地向感测线施加偏置电压来减小应力。字线连接到反相器件，反相器件又连接到有效地将存储器单元中的可变阈值可编程晶体管的栅极接地的晶体管。字线的掉电反映在感测线的同步掉电中。此外，在断电时，用于特定核心存储器单元的读出放大器与主锁存电路断开，主锁存电路又连接到从锁存电路，用于将先前的读出放大器输出施加到输入/输出缓冲器，以便在读取操作期间保护在核心存储器中感测的数据。本发明还允许在感测线和可变阈值可编程晶体管的擦除操作期间减少字线电压。

9. 发明授权

US5390147A Core organization and sense amplifier having lubricating current, active clamping and buffered sense node for speed enhancement for non-volatile memory 失效
标题翻译：具有润滑电流，有源钳位和缓冲感测节点的核心组织和读出放大器，用于非易失性存储器的速度增强
公开(公告)号：US5390147A
公开(公告)日：1995-02-14
申请号：US204866
申请日：1994-03-02
申请人： George Smarandoiu , Emil Lambrache
发明人： George Smarandoiu , Emil Lambrache
IPC分类号： G11C17/00 , G11C7/06 , G11C7/14 , G11C16/06 , G11C11/40
CPC分类号： G11C7/062 , G11C7/14
摘要： Sense amplifier performance is improved in a sense amplifier circuit connected to a semiconductor memory. A current mirror circuit is connected to a data node on the side of a pass transistor adjacent to core memory. The other side of the current mirror circuit is connected to modify the current provided from a memory reference cell. This provides a lubricating current to the pass transistor to ensure that it does not shut down in the absence of current flow from a core memory cell. Sense amplifier speed is improved by a higher transconductance level in the pass transistors. Speed is improved by reducing sense node capacitance through buffer circuitry. Core performance is enhanced by interspersed reference columns within the core at distributed locations.
摘要翻译：在连接到半导体存储器的读出放大器电路中，感测放大器性能得到改善。电流镜电路连接到与核心存储器相邻的传输晶体管侧的数据节点。连接电流镜电路的另一侧来修改从存储器参考单元提供的电流。这为通过晶体管提供润滑电流，以确保在没有来自核心存储单元的电流流动的情况下它不会关闭。传感放大器的速度通过传导晶体管中较高的跨导电平来提高。通过缓冲电路减少感测节点电容来提高速度。分布式位置核心内散布的参考列可增强核心性能。

10. 发明授权

US5765185A EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles 失效
标题翻译：具有闪存芯的EEPROM阵列具有ECC或写缓存或可中断的负载周期
公开(公告)号：US5765185A
公开(公告)日：1998-06-09
申请号：US714605
申请日：1996-09-16
申请人： Emil Lambrache , George Smarandoiu
发明人： Emil Lambrache , George Smarandoiu
IPC分类号： G11C16/02 , G06F11/10 , G06F12/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C29/42 , G06F12/16
CPC分类号： G06F11/1068 , G06F12/0893 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3431 , G06F11/1008 , G06F2212/2022
摘要： A sector programmable EEPROM memory capable of emulating the byte programmable functionality of full-featured byte programmable EEPROMs. The EEPROM memory incorporates an on-chip write cache used as a buffer between byte level data entered by the user system and word level data written to the main memory core. The EEPROM main memory core is divided into memory pages with each memory page further divided into sub-page sectors, and each sub-page sector holding a multitude of multi-byte data words. The sub-page sectors within a memory page can be individually or collectively subjected to a program and erase cycle. The EEPROM memory incorporates an ECC unit used to recover and refresh lost data in the memory core. The EEPROM memory is also capable of interruptible load cycles.
摘要翻译：一个扇区可编程EEPROM存储器，能够仿真全功能字节可编程EEPROM的字节可编程功能。 EEPROM存储器包含用作用户系统输入的字节级数据与写入主存储器核心的字电平数据之间的缓冲器的片上写缓存。 EEPROM主存储器核心被分成存储器页，每个存储器页进一步分成子页扇区，每个子页扇区保持多个多字节数据字。存储器页面内的子页面扇区可以单独地或共同地进行编程和擦除循环。 EEPROM存储器包含用于恢复和刷新存储器核心中的丢失数据的ECC单元。 EEPROM存储器还能够中断负载周期。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式