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1. 发明授权

US09922157B1 Sector-based clock routing methods and apparatus 有权
公开(公告)号：US09922157B1
公开(公告)日：2018-03-20
申请号：US14802702
申请日：2015-07-17
申请人： Altera Corporation
发明人： Carl Ebeling , Herman Henry Schmit , Dana How , Mahesh A. Iyer , Saurabh Adya
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

2. 发明授权

US09813061B1 Circuitry for implementing multi-mode redundancy and arithmetic functions 有权
公开(公告)号：US09813061B1
公开(公告)日：2017-11-07
申请号：US15150869
申请日：2016-05-10
申请人： Altera Corporation
发明人： Herman Henry Schmit , David Lewis
IPC分类号： H03K19/003 , G06F7/501 , H03K19/23 , H03K19/007 , G06F11/20
CPC分类号： H03K19/00392 , G06F7/501 , G06F11/187 , G06F11/2089 , G06F11/2094 , H03K19/00369 , H03K19/0075 , H03K19/23
摘要： Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

3. 发明申请

US20170041249A1 Programmable Logic Device With Integrated Network-On-Chip 审中-公开
标题翻译：集成片上系统的可编程逻辑器件
公开(公告)号：US20170041249A1
公开(公告)日：2017-02-09
申请号：US15298122
申请日：2016-10-19
申请人： Altera Corporation
发明人： Michael David Hutton , Herman Henry Schmit , Dana How
IPC分类号： H04L12/933 , H04L12/927 , H04L12/24
CPC分类号： H04L49/109 , G06F15/7825 , H04L41/0893 , H04L41/12 , H04L47/805
摘要： Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.
摘要翻译：用于在集成电路上提供用于高速数据传输的片上网络（NoC）结构的系统和方法。在某些方面，NoC结构包括具有与集成电路的本地组件的双向连接的硬IP接口的多个NoC站。在某些方面，NoC站具有支持NoC站的硬IP接口的软IP接口。

4. 发明授权

US09553762B1 Network-on-chip with fixed and configurable functions 有权
标题翻译：具有固定和可配置功能的片上网络
公开(公告)号：US09553762B1
公开(公告)日：2017-01-24
申请号：US14316433
申请日：2014-06-26
申请人： Altera Corporation
发明人： Dana How , Herman Henry Schmit , Sean R. Atsatt
IPC分类号： H04L12/50 , H04L12/24
CPC分类号： H04L45/06
摘要： Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.
摘要翻译：本文提供的系统和方法用于提供包括可配置的节点阵列的NoC，其中节点的可配置阵列的节点以默认操作模式运行，直到触发替换操作模式。例如，当NoC未被配置时，可以将锁存库初始化为“清除”，使得不存储路由决定。这可以启用默认操作模式，其中路由逻辑根据需要更新锁存器的值，以便以动态方式实现所需的路由行为，直到执行配置。

5. 发明授权

US09300421B2 Methods to achieve accurate time stamp in IEEE 1588 for system with FEC encoder 有权
标题翻译：在具有FEC编码器的系统的IEEE 1588中实现精确时间戳的方法
公开(公告)号：US09300421B2
公开(公告)日：2016-03-29
申请号：US14058718
申请日：2013-10-21
申请人： Altera Corporation
发明人： Haiyun Yang , David W. Mendel , Keith Duwel , Huy Ngo , Herman Henry Schmit
IPC分类号： H04J3/06
CPC分类号： H04J3/0697 , H04J3/0667 , H04L1/0042
摘要： Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.
摘要翻译：公开了用于允许集成电路或设备内的通信系统中的介质访问控制（MAC）层在例如精确时间协议（PTP）协议时准确地确定时间戳点和时间戳值的系统和方法和系统正在由通信系统使用。通信系统可以使用精确时间戳点和时间戳值的这种确定来解释并补偿由MAC层发送的数据帧中的前向纠错（FEC）子层改变的时间偏移。从FEC向MAC提供反馈，以允许MAC将数据帧的时间戳点和时间戳值对齐前导码精确地确定到由FEC子层输出的FEC比特块的开头。

6. 发明授权

US10289483B2 Methods and apparatus for embedding an error correction code in storage circuits 有权
公开(公告)号：US10289483B2
公开(公告)日：2019-05-14
申请号：US15251951
申请日：2016-08-30
申请人： Altera Corporation
发明人： Herman Henry Schmit , Michael David Hutton
IPC分类号： G11C29/00 , G06F11/10 , H03M13/05 , G06F11/07 , G11C29/52
摘要： A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.

7. 发明授权

US10141936B2 Pipelined interconnect circuitry with double data rate interconnections 有权
公开(公告)号：US10141936B2
公开(公告)日：2018-11-27
申请号：US15630436
申请日：2017-06-22
申请人： Altera Corporation
发明人： David Lewis , Herman Henry Schmit , Carl Ebeling
IPC分类号： H03K19/0175 , H03K19/173 , H03K19/0185
摘要： An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

8. 发明授权

US09740808B2 Method and apparatus for implementing a system-level design tool for design planning and architecture exploration 有权
公开(公告)号：US09740808B2
公开(公告)日：2017-08-22
申请号：US15335012
申请日：2016-10-26
申请人： Altera Corporation
发明人： Michael David Hutton , Herman Henry Schmit
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/50 , G06F17/5036 , G06F17/5045 , G06F17/5054 , G06F2217/06
摘要： A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.

9. 发明授权

US09507883B2 Method and apparatus for implementing a system-level design tool for design planning and architecture exploration 有权
标题翻译：用于实施设计规划和架构探索的系统级设计工具的方法和装置
公开(公告)号：US09507883B2
公开(公告)日：2016-11-29
申请号：US13925764
申请日：2013-06-24
申请人： Altera Corporation
发明人： Michael David Hutton , Herman Henry Schmit
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/50 , G06F17/5036 , G06F17/5045 , G06F17/5054 , G06F2217/06
摘要： A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
摘要翻译：用于在目标设备上设计系统的方法包括在产生系统的寄存器传送级别描述之前，将系统的高级描述映射到目标设备的模型上。生成映射的视觉表示。

10. 发明申请

US20160294413A1 METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN MEMORY CELLS 有权
标题翻译：用于嵌入存储单元中的错误校正码的方法和装置
公开(公告)号：US20160294413A1
公开(公告)日：2016-10-06
申请号：US14675294
申请日：2015-03-31
申请人： Altera Corporation
发明人： Herman Henry Schmit , Michael David Hutton
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： G06F11/1068 , G06F11/0787 , G06F11/1004 , G06F11/1012 , G06F11/1044 , G06F17/5054 , G11C29/52 , H03M13/05
摘要： A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.
摘要翻译：计算机辅助设计（CAD）工具可以识别配置数据中的无关位。不关心配置数据中的位可能会改变极性，而不影响电路设计的功能。 CAD工具可以计算错误校验码（例如，用于二维奇偶校验的奇偶校验位），并将错误校验码插入到配置数据中。作为示例，CAD工具可以用错误代码替代配置数据中的无关位。配置数据可以存储在可编程集成电路上的配置存储器单元中，从而在可编程集成电路上实现具有错误代码的电路设计。在执行期间，可编程集成电路可以基于嵌入的错误代码执行错误检查并检测和纠正配置数据中的错误。

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