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1. 发明授权

US11294842B2 Multichip package with protocol-configurable data paths 有权
公开(公告)号：US11294842B2
公开(公告)日：2022-04-05
申请号：US17131474
申请日：2020-12-22
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
IPC分类号： G06F13/40 , G06F5/06 , G06F13/42
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

2. 发明申请

US20200065282A1 MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS 审中-公开
公开(公告)号：US20200065282A1
公开(公告)日：2020-02-27
申请号：US16436771
申请日：2019-06-10
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
IPC分类号： G06F13/40 , G06F13/42 , G06F5/06
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

3. 发明公开

US20230289309A1 MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS 审中-公开
公开(公告)号：US20230289309A1
公开(公告)日：2023-09-14
申请号：US18306100
申请日：2023-04-24
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
IPC分类号： G06F13/40 , G06F13/42 , G06F5/06
CPC分类号： G06F13/4022 , G06F5/065 , G06F13/4018 , G06F13/4291 , G06F2205/067
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

4. 发明授权

US10884964B2 Multichip package with protocol-configurable data paths 有权
公开(公告)号：US10884964B2
公开(公告)日：2021-01-05
申请号：US16436771
申请日：2019-06-10
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
IPC分类号： G06F13/40 , G06F5/06 , G06F13/42
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

5. 发明申请

US20220222193A1 MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS 有权
公开(公告)号：US20220222193A1
公开(公告)日：2022-07-14
申请号：US17711860
申请日：2022-04-01
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
IPC分类号： G06F13/40 , G06F13/42 , G06F5/06
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

6. 发明授权

US10009198B2 Configurable multi-lane scrambler for flexible protocol support 有权
公开(公告)号：US10009198B2
公开(公告)日：2018-06-26
申请号：US15167785
申请日：2016-05-27
申请人： Altera Corporation
发明人： Curt Wortman , Chong H. Lee , Huy Ngo
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00 , G06F13/12 , G06M3/00 , G11C19/00 , G01R31/28 , G06F17/50 , G06F1/02 , G06F7/58 , H04L9/00 , H04L25/03 , G06F13/40 , G06F13/42 , G11C7/10 , G11C19/28
CPC分类号： H04L25/03866 , G06F3/00 , G06F5/00 , G06F7/58 , G06F13/00 , G06F13/12 , G06F13/40 , G06F13/4221 , G06F13/4282 , G11C7/1012 , G11C7/1036 , G11C19/00 , G11C19/285 , H04L9/00
摘要： Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

7. 发明申请

US20140269778A1 METHODS TO ACHIEVE ACCURATE TIME STAMP IN IEEE 1588 FOR SYSTEM WITH FEC ENCODER 有权
标题翻译：采用FEC编码器的IEEE 1588系统中实现精确时间戳的方法
公开(公告)号：US20140269778A1
公开(公告)日：2014-09-18
申请号：US14058718
申请日：2013-10-21
申请人： Altera Corporation
发明人： Haiyun Yang , David W. Mendel , Keith Duwel , Huy Ngo , Herman Henry Schmit
IPC分类号： H04J3/06
CPC分类号： H04J3/0697 , H04J3/0667 , H04L1/0042
摘要： Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.
摘要翻译：公开了用于允许集成电路或设备内的通信系统中的介质访问控制（MAC）层在例如精确时间协议（PTP）协议时准确地确定时间戳点和时间戳值的系统和方法和系统正在由通信系统使用。通信系统可以使用精确时间戳点和时间戳值的这种确定来解释并补偿由MAC层发送的数据帧中的前向纠错（FEC）子层改变的时间偏移。从FEC向MAC提供反馈，以允许MAC将数据帧的时间戳点和时间戳值对齐前导码精确地确定到由FEC子层输出的FEC比特块的开头。

8. 发明授权

US11669479B2 Multichip package with protocol-configurable data paths 有权
公开(公告)号：US11669479B2
公开(公告)日：2023-06-06
申请号：US17711860
申请日：2022-04-01
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
IPC分类号： G06F13/40 , G06F13/42 , G06F5/06
CPC分类号： G06F13/4022 , G06F5/065 , G06F13/4018 , G06F13/4291 , G06F2205/067
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

9. 发明申请

US20210109882A1 MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS 有权
公开(公告)号：US20210109882A1
公开(公告)日：2021-04-15
申请号：US17131474
申请日：2020-12-22
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , David W. Mendel
IPC分类号： G06F13/40 , G06F5/06 , G06F13/42
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

10. 发明申请

US20180034748A1 MULTI-FUNCTION, MULTI-PROTOCOL FIFO FOR HIGH-SPEED COMMUNICATION 审中-公开
公开(公告)号：US20180034748A1
公开(公告)日：2018-02-01
申请号：US15676402
申请日：2017-08-14
申请人： Altera Corporation
发明人： Huy Ngo , Keith Duwel , Vinson Chan , Divya Vijayaraghavan , Curt Wortman
IPC分类号： H04L12/861 , H04L12/863
CPC分类号： H04L49/90 , H04L47/6245
摘要： Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

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