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1. 发明授权

US09362913B1 Circuitry for implementing multi-mode redundancy and arithmetic functions 有权
标题翻译：实现多模冗余和算术功能的电路
公开(公告)号：US09362913B1
公开(公告)日：2016-06-07
申请号：US14499006
申请日：2014-09-26
申请人： Altera Corporation
发明人： Herman Henry Schmit , David Lewis
IPC分类号： H03K19/003 , H03K19/23 , H03K19/007 , G06F11/20
CPC分类号： H03K19/00392 , G06F7/501 , G06F11/187 , G06F11/2089 , G06F11/2094 , H03K19/00369 , H03K19/0075 , H03K19/23
摘要： Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.
摘要翻译：诸如专用集成电路或可编程逻辑器件的集成电路可以包括多个配对电路的多个副本以及有时也被称为多模冗余的配置的多数投票电路。加法器电路可以耦合到这些多个拷贝，并且基于从多个拷贝接收的信号产生进位信号和和信号。加法器电路的进位信号可以提供多数投票操作的结果。逻辑异或门可以在和信号和进位信号之间执行逻辑异或运算，从而产生误差信号。错误信号可以指示多个副本之一产生与其他副本产生的输出不同的输出。

2. 发明授权

US09164826B2 Method and apparatus to recover from an erroneous logic state in an electronic system 有权
标题翻译：从电子系统中的错误逻辑状态恢复的方法和装置
公开(公告)号：US09164826B2
公开(公告)日：2015-10-20
申请号：US13747870
申请日：2013-01-23
申请人： Devon Fernandez
发明人： Devon Fernandez
IPC分类号： G06F11/07 , G06F11/08 , G05B19/045 , G05B19/4063 , G06F11/10 , B60G17/0185 , H03K17/24 , H03K19/007 , H03K19/003
CPC分类号： G06F11/08 , B60G17/0185 , G05B19/045 , G05B19/4063 , G06F11/0793 , G06F11/0796 , G06F11/102 , G06F11/1032 , H03K17/24 , H03K19/00392 , H03K19/007
摘要： An electronic system includes circuitry to detect errors in logic state in the system and to initiate corrective action when one or more errors are detected. In some embodiments, redundant information is stored within a system that is associated with an operational state of the system. If the operational state of the system is subsequently corrupted as a result of an electrical or mechanical overstress condition, resulting errors may be detected by comparing or otherwise processing the stored operational state information and the redundant information.
摘要翻译：电子系统包括用于检测系统中的逻辑状态中的错误并在检测到一个或多个错误时启动校正动作的电路。在一些实施例中，冗余信息存储在与系统的操作状态相关联的系统内。如果系统的运行状态随后由于电或机械过载状态而被破坏，则可以通过比较或以其他方式处理所存储的操作状态信息和冗余信息来检测所产生的错误。

3. 发明申请

US20150169400A1 MEMORY CIRCUIT INCORPORATING RADIATION-HARDENED MEMORY SCRUB ENGINE 有权
标题翻译：存储电路与辐射硬化存储器发动机
公开(公告)号：US20150169400A1
公开(公告)日：2015-06-18
申请号：US14635880
申请日：2015-03-02
申请人： SILICON SPACE TECHNOLOGY CORPORATION
发明人： WESLEY H. MORRIS , DAVID R. GIFFORD , REX E. LOWTHER
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/0793 , G06F11/1048 , G06F11/183 , G06F11/186 , G11C8/00 , H03K19/00392
摘要： An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.
摘要翻译：示例性集成电路包括包括第一多个数据组的第一存储器阵列，每个这样的数据组包括相应的多个数据位。集成电路还包括被配置为检测和校正从第一存储器阵列读取的数据组中的错误的第一错误检测和校正（EDAC）电路。该集成电路还包括第一擦除电路，其被配置为按顺序访问第一多个数据组中的每个数据组以校正其中检测到的任何错误。第一EDAC电路和第一擦洗电路都包括空间冗余电路。第一EDAC电路和第一擦除电路可以包括掩埋保护环（BGR）结构，并且可以包括寄生隔离装置（PID）结构。空间冗余电路可以包括双重互锁存储单元（DICE）电路，并且可以包括时间滤波电路。

4. 发明授权

US09036392B2 Redundancy circuit for reducing chip area 有权
标题翻译：用于减少芯片面积的冗余电路
公开(公告)号：US09036392B2
公开(公告)日：2015-05-19
申请号：US13207650
申请日：2011-08-11
申请人： Heung-Taek Oh
发明人： Heung-Taek Oh
IPC分类号： G11C17/00 , H03K19/003 , G11C29/00 , G11C17/16
CPC分类号： H03K19/00392 , G11C17/16 , G11C29/787
摘要： A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array.
摘要翻译：冗余电路包括多个块地址线，存储第一数据的第一熔丝阵列，多个第一本地线，其被配置为响应于所述第一熔丝阵列中的相应线的信号，向第一熔丝阵列提供验证电压块地址线，存储第二数据的第二熔丝阵列，多个第二本地线，被配置为响应于所述多个块地址线中的对应线的信号而将验证电压提供给所述第二熔丝阵列，以及多个被配置为检查第一熔丝阵列的第一数据和第二熔丝阵列的第二数据的验证线，其中多个验证线由第一熔丝阵列和第二熔丝阵列共享，并且设置在第一熔丝阵列和第二保险丝阵列。

5. 发明申请

US20140372817A1 AUTOMATED CIRCUIT TRIPLICATION METHOD AND SYSTEM 有权
标题翻译：自动电路三维方法和系统
公开(公告)号：US20140372817A1
公开(公告)日：2014-12-18
申请号：US14308471
申请日：2014-06-18
申请人： Brigham Young University
发明人： Michael J. Wirthlin
IPC分类号： G06F11/16
CPC分类号： G06F11/1608 , G06F17/5054 , H03K19/00392 , H03K19/23
摘要： In one general aspect, a non-transitory computer-readable storage medium can be configured to store instructions that when executed cause a processor to perform a process. The process can include defining a plurality of subsets from a representation of a circuit, and rank-ordering each subset from the plurality of subsets. The process can also include selecting at least one of the subsets for triplication based on the rank-ordering and a triplication condition.
摘要翻译：在一个一般方面，非暂时计算机可读存储介质可以被配置为存储当被执行时引起处理器执行处理的指令。该过程可以包括从电路的表示中定义多个子集，并且从多个子集中对每个子集进行排序排序。该过程还可以包括基于等级排序和三重条件来选择子集中的至少一个以进行三次重复。

6. 发明申请

US20140139263A1 DATA PROCESSING APPARATUS AND METHOD IN PLC SYSTEM 有权
标题翻译： PLC系统中的数据处理设备和方法
公开(公告)号：US20140139263A1
公开(公告)日：2014-05-22
申请号：US14062258
申请日：2013-10-24
申请人： LSIS CO., LTD.
发明人： Jo Dong PARK
IPC分类号： H03K19/003
CPC分类号： H03K19/00392 , G05B19/054
摘要： A programmable logic controller (PLC) system, and more particularly, a data processing apparatus and method in the PLC system are provided. In the data processing method in a programmable logic controller (PLC) system, first dummy code data is output to an area having a chip selection signal for valid data output. The valid data is output after the first dummy code data is output. And second dummy code data is output when the valid data output is completed.
摘要翻译：提供了一种可编程逻辑控制器（PLC）系统，更具体地说，提供了一种PLC系统中的数据处理装置和方法。在可编程逻辑控制器（PLC）系统的数据处理方法中，将第一虚拟代码数据输出到具有用于有效数据输出的芯片选择信号的区域。在输出第一个虚拟代码数据之后输出有效数据。并且当有效的数据输出完成时输出第二个虚拟代码数据。

7. 发明授权

US08704226B2 Three-dimensional integrated circuit having redundant relief structure for chip bonding section 有权
标题翻译：具有用于芯片接合部分的冗余浮雕结构的三维集成电路
公开(公告)号：US08704226B2
公开(公告)日：2014-04-22
申请号：US13812011
申请日：2012-01-11
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： H01L23/58
CPC分类号： H01L23/49527 , H01L22/22 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L27/0688 , H01L2224/13009 , H01L2224/13147 , H01L2224/16147 , H01L2224/16225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/3511 , H03K19/00392 , H01L2924/00014 , H01L2924/00
摘要： A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset.
摘要翻译：芯片层叠在重新布线构件上。多个连接构件和多个冗余连接构件布置在芯片中，并将芯片电连接到重新布线构件。冗余电路嵌入在每个重新布线构件和芯片中。当其中一个连接构件故障时，冗余电路使冗余连接构件中的一个在重新布线构件和芯片之间传递信号，而不是错误的连接构件。连接构件具有分别布置在第一和第二区域中的第一和第二子集。与第二区域相比，重新布线构件和芯片之间的距离超过了第一区域中的预定阈值。第一子集具有较高比例的连接构件，冗余电路可以用冗余连接构件的子集替代第二子集。

8. 发明授权

US08680885B1 Low leakage logic circuit 有权
标题翻译：低泄漏逻辑电路
公开(公告)号：US08680885B1
公开(公告)日：2014-03-25
申请号：US13686002
申请日：2012-11-27
申请人： Valter Karavanic , Gary Hau
发明人： Valter Karavanic , Gary Hau
IPC分类号： H03K17/16 , H03K19/003 , H03K19/23
CPC分类号： H03K19/001 , H03K19/00392
摘要： A low leakage logic circuit. The low leakage logic circuit includes a control circuit for logic circuit. The control circuit has a first transistor, a second transistor, a third transistor, a first diode, a first resistor and a second resistor. When the control circuit is ON, a first circuit path in the logic circuit is supplied with a first voltage from the source terminal of the third transistor. This voltage acts as a logic output and has the ability to source current at output terminal of the logic circuit. When the control circuit is OFF, a second circuit path in the logic circuit is supplied with a second voltage from the control circuit which is lower than the turn-on voltage of the second circuit path. This voltage is insufficient to turn ON the logic circuit, hence no current flows into the logic circuit.
摘要翻译：低泄漏逻辑电路。低泄漏逻辑电路包括用于逻辑电路的控制电路。控制电路具有第一晶体管，第二晶体管，第三晶体管，第一二极管，第一电阻器和第二电阻器。当控制电路为ON时，从第三晶体管的源极端子向逻辑电路中的第一电路提供第一电压。该电压用作逻辑输出，并具有在逻辑电路的输出端输出电流的能力。当控制电路断开时，向控制电路提供逻辑电路中的第二电路，该第二电压低于第二电路路径的接通电压。该电压不足以导通逻辑电路，因此没有电流流入逻辑电路。

9. 发明申请

US20130279242A1 VOLATILE MEMORY ELEMENTS WITH SOFT ERROR UPSET IMMUNITY 有权
标题翻译：具有软错误UPS易失性的易失性存储器元件
公开(公告)号：US20130279242A1
公开(公告)日：2013-10-24
申请号：US13924389
申请日：2013-06-21
申请人： Altera Corporation
发明人： Bruce B. Pedersen
IPC分类号： G11C11/412
CPC分类号： G11C11/412 , G11C7/20 , G11C11/4125 , H03K19/00392 , H03K19/177 , H03K19/1776 , H03K19/17764
摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.
摘要翻译：提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。存储元件可以各自具有十个晶体管，其包括互连以形成双稳态元件的两个地址晶体管和四个晶体管对。诸如真实和补充清除线之类的清除线可以被路由到与某些晶体管对相关联的正电源端子和接地电源端子。在清除操作期间，可以使用清除线选择性地削弱部分或全部晶体管对。这有助于明确的操作，其中逻辑零值通过地址晶体管驱动并且减小交叉电流浪涌。

10. 发明授权

US08502556B2 System and method for reducing input current spike for drive circuitry 有权
标题翻译：用于减少驱动电路的输入电流尖峰的系统和方法
公开(公告)号：US08502556B2
公开(公告)日：2013-08-06
申请号：US13341317
申请日：2011-12-30
申请人： Yann Desprez-Le-Goarant , Jingfeng Gong
发明人： Yann Desprez-Le-Goarant , Jingfeng Gong
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361 , G06F3/0416 , H03K19/00392
摘要： A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display.
摘要翻译：电路包括多个逻辑门和驱动电路。多个逻辑门耦合在第一供应节点和第二供应节点之间。每个逻辑门具有至少一个输入，并在逻辑状态转换期间消耗短路电流。驱动电路耦合到多个逻辑门的输入，以将输入信号的副本传送到每个逻辑门，其中输入信号复制在基本上不同的时间到达逻辑门的输入端。电路可以结合在触摸屏面板和显示器中。

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