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1. 发明授权

US10572262B2 Register mapping of register specifiers to registers depending on a key value used for mapping at least two of the register specifiers 有权
公开(公告)号：US10572262B2
公开(公告)日：2020-02-25
申请号：US15651158
申请日：2017-07-17
申请人： ARM LIMITED
发明人： Jocelyn Francois Orion Jaubert , Frederic Jean Denis Arsanto , Guillaume Schon , Carlo Dario Fanara
IPC分类号： G06F9/38 , G06F9/30
摘要： An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

2. 发明授权

US09323536B2 Identification of missing call and return instructions for management of a return address stack 有权
标题翻译：识别返回地址堆栈的管理的缺失调用和返回指令
公开(公告)号：US09323536B2
公开(公告)日：2016-04-26
申请号：US13875704
申请日：2013-05-02
申请人： ARM LIMITED
发明人： Clement Marc Demongeot , Louis-Marie Vincent Mouton , Jocelyn Francois Orion Jaubert
IPC分类号： G06F9/00 , G06F9/44 , G06F9/34 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30054 , G06F9/3806
摘要： A data processing apparatus and method of data processing are disclosed. A fetch unit retrieves program instructions comprising call instructions and return instructions from memory to be executed by an execution unit. A branch prediction unit generates a return address prediction for an identified return instruction with reference to a return address stack. The branch prediction unit performs a return address push onto said return address stack when the execution unit executes a call instruction and performs a return address pop from the return address stack when the execution unit executes a return instruction. An error detection unit identifies a missing call instruction or a missing return instruction in said program instructions by reference to the return address prediction, a resolved return address indicated by the execution unit when the return instruction is executed and the content of the return address stack.
摘要翻译：公开了一种数据处理装置和数据处理方法。提取单元检索包括来自存储器的调用指令和返回指令以由执行单元执行的程序指令。分支预测单元参考返回地址堆栈生成针对所标识的返回指令的返回地址预测。当执行单元执行呼叫指令并且当执行单元执行返回指令时，从返回地址堆栈执行返回地址弹出时，分支预测单元执行到所述返回地址堆栈的返回地址推送。错误检测单元通过参考返回地址预测来识别所述程序指令中的缺失的调用指令或缺少的返回指令，当执行返回指令时由执行单元指示的解析返回地址和返回地址堆栈的内容。

3. 发明授权

US10540299B2 Resetting operating state holding element 有权
公开(公告)号：US10540299B2
公开(公告)日：2020-01-21
申请号：US15638524
申请日：2017-06-30
申请人： ARM LIMITED
发明人： Carlo Dario Fanara , Frederic Jean Denis Arsanto , Guillaume Schon , Jocelyn Francois Orion Jaubert
IPC分类号： G06F9/44 , G06F12/14 , G06F9/4401 , G06F9/24 , G06F1/24 , G06F9/30
摘要： An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

4. 发明授权

US09361112B2 Return address prediction 有权
标题翻译：返回地址预测
公开(公告)号：US09361112B2
公开(公告)日：2016-06-07
申请号：US13865371
申请日：2013-04-18
申请人： ARM Limited
发明人： Clément Marc Demongeot , Louis-Marie Vincent Mouton , Frédéric Claude Marie Piry , Jocelyn Francois Orion Jaubert , Albin Pierick Tonnerre
IPC分类号： G06F9/30 , G06F7/38 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute instructions in dependence on a predicted outcome of earlier instructions and a return address prediction unit is configured to store return addresses associated with unresolved call instructions. The return address prediction unit comprises: a stack portion onto which return addresses associated with unresolved call instructions are pushed, and from which a return address is popped when a return instruction is speculatively executed; and a buffer portion which stores an entry for each unresolved call instruction executed and for each return instruction which is speculatively executed.
摘要翻译：数据处理装置执行呼叫指令，并且在响应于呼叫指令执行的指令序列之后，返回指令使程序流程返回到与该呼叫指令相关联的程序序列中的一个点。数据处理装置被配置为根据早期指令的预测结果推测执行指令，并且返回地址预测单元被配置为存储与未解决的呼叫指令相关联的返回地址。返回地址预测单元包括：堆栈部分，在其上推送与未解决的呼叫指令相关联的返回地址，并且当推测性地执行返回指令时从该地址弹出返回地址; 以及缓冲部分，其存储针对执行的每个未解决的调用指令的条目和针对被推测执行的每个返回指令。

5. 发明授权

US09513925B2 Marking long latency instruction as branch in pending instruction table and handle as mis-predicted branch upon interrupting event to return to checkpointed state 有权
标题翻译：将长延迟指令标记为待处理指令表中的分支，并在中断事件返回到检查点状态时处理为误预测分支
公开(公告)号：US09513925B2
公开(公告)日：2016-12-06
申请号：US14031281
申请日：2013-09-19
申请人： ARM LIMITED
发明人： Nicolas Chaussade , Florent Begon , Melanie Emanuelle Lucie Teyssier , Remi Teyssier , Jocelyn Francois Orion Jaubert
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/30145 , G06F9/3842 , G06F9/3863
摘要： A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction.
摘要翻译：提供数据处理装置和数据处理方法。该数据处理装置包括被配置为执行程序指令序列的执行电路。检查点电路被配置为识别程序指令序列中的预定类型的指令的实例，并且存储与该实例相关联的检查点信息。检查点信息在执行预定类型的指令的该实例之前识别数据处理装置的状态，其中预定类型的指令具有期望的长完成延迟。如果执行电路由于发生预定事件而没有完成预定类型的指令的实例的执行，则数据处理装置被配置为参照检查点信息恢复数据处理装置的状态，使得然后，执行电路被配置为在预定类型的指令的那个情况下重新开始执行程序指令的序列。

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