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1. 发明授权

US07836285B2 Implementation of variable length instruction encoding using alias addressing 有权
标题翻译：使用别名寻址实现可变长度指令编码
公开(公告)号：US07836285B2
公开(公告)日：2010-11-16
申请号：US11890907
申请日：2007-08-08
申请人： Abhijit Giri , Rajiv Nadig
发明人： Abhijit Giri , Rajiv Nadig
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30149 , G06F9/30196 , G06F9/3802 , G06F12/04
摘要： A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.
摘要翻译：数字处理器和操作方法利用别名地址空间来实现传统处理器上的可变长度指令编码。该方法包括将代码序列的指令存储在存储器中; 生成代码序列的指令地址; 响应于第一地址空间和第二地址空间之间的指令地址的转变，自动地在第一操作模式和第二操作模式之间切换，其中第一和第二地址空间中的地址访问公共存储器空间; 在第一操作模式下，访问第一地址空间中的指令; 在第二操作模式中，访问第二地址空间中的指令; 并执行代码序列的所访问的指令。可以在第一和第二操作模式中使用不同指令长度的指令。

2. 发明申请

US20090043990A1 Implementation of variable length instruction encoding using alias addressing 有权
标题翻译：使用别名寻址实现可变长度指令编码
公开(公告)号：US20090043990A1
公开(公告)日：2009-02-12
申请号：US11890907
申请日：2007-08-08
申请人： Abhijit Giri , Rajiv Nadig
发明人： Abhijit Giri , Rajiv Nadig
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30189 , G06F9/30149 , G06F9/30196 , G06F9/3802 , G06F12/04
摘要： A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.
摘要翻译：数字处理器和操作方法利用别名地址空间来实现传统处理器上的可变长度指令编码。该方法包括将代码序列的指令存储在存储器中; 生成代码序列的指令地址; 响应于第一地址空间和第二地址空间之间的指令地址的转变，自动地在第一操作模式和第二操作模式之间切换，其中第一和第二地址空间中的地址访问公共存储器空间; 在第一操作模式下，访问第一地址空间中的指令; 在第二操作模式中，访问第二地址空间中的指令; 并执行代码序列的所访问的指令。可以在第一和第二操作模式中使用不同指令长度的指令。

3. 发明授权

US08332621B2 Implementation of variable length instruction encoding using alias addressing 有权
标题翻译：使用别名寻址实现可变长度指令编码
公开(公告)号：US08332621B2
公开(公告)日：2012-12-11
申请号：US12900993
申请日：2010-10-08
申请人： Abhijit Giri , Rajiv Nadig
发明人： Abhijit Giri , Rajiv Nadig
IPC分类号： G06F9/26
CPC分类号： G06F9/30189 , G06F9/30149 , G06F9/30196 , G06F9/3802 , G06F12/04
摘要： A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.
摘要翻译：数字处理器和操作方法利用别名地址空间来实现传统处理器上的可变长度指令编码。该方法包括将代码序列的指令存储在存储器中; 生成代码序列的指令地址; 响应于第一地址空间和第二地址空间之间的指令地址的转变，自动地在第一操作模式和第二操作模式之间切换，其中第一和第二地址空间中的地址访问公共存储器空间; 在第一操作模式下，访问第一地址空间中的指令; 在第二操作模式中，访问第二地址空间中的指令; 并执行代码序列的所访问的指令。可以在第一和第二操作模式中使用不同指令长度的指令。

4. 发明申请

US20110078423A1 IMPLEMENTATION OF VARIABLE LENGTH INSTRUCTION ENCODING USING ALIAS ADDRESSING 有权
标题翻译：使用ALIAS寻址实现可变长度指令编码
公开(公告)号：US20110078423A1
公开(公告)日：2011-03-31
申请号：US12900993
申请日：2010-10-08
申请人： Abhijit Giri , Rajiv Nadig
发明人： Abhijit Giri , Rajiv Nadig
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/30149 , G06F9/30196 , G06F9/3802 , G06F12/04
摘要： A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.
摘要翻译：数字处理器和操作方法利用别名地址空间来实现传统处理器上的可变长度指令编码。该方法包括将代码序列的指令存储在存储器中; 生成代码序列的指令地址; 响应于第一地址空间和第二地址空间之间的指令地址的转变，自动地在第一操作模式和第二操作模式之间切换，其中第一和第二地址空间中的地址访问公共存储器空间; 在第一操作模式下，访问第一地址空间中的指令; 在第二操作模式中，访问第二地址空间中的指令; 并执行代码序列的所访问的指令。可以在第一和第二操作模式中使用不同指令长度的指令。

5. 发明授权

US07206927B2 Pipelined processor method and circuit with interleaving of iterative operations 有权
公开(公告)号：US07206927B2
公开(公告)日：2007-04-17
申请号：US10299412
申请日：2002-11-19
申请人： Abhijit Giri
发明人： Abhijit Giri
IPC分类号： G06F7/38
CPC分类号： G06F9/3851 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/3867
摘要： A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction stream; interleaving p steams of instances of the instruction in the pipeline; detecting an end of the iteration; and combining results obtained from the p streams after all programmed iterations have completed. A computational circuit comprises a register which can hold a value representing both an operand and result of an iterative operation; a multiplexer having a first input connected to receive the operand from the register, a second input connected to a source of an identify value for the iterative operation, and an output; and an operator circuit having an input connected to receive a value from the multiplexer output, and an output connected to return thee result to the register. A method of executing an instruction stream in a pipelined execution unit comprises providing to the execution unit the instruction stream as a sequence of instruction in natural order absent software scheduling; detecting an iteration of an instruction in the sequence of instruction; and introducing into a pipeline of the pipelined execution unit plural instances of the iterated instruction, each with different data. A method of executing an instruction stream in a pipelined execution unit comprises detecting an iteration of an instruction in the instruction stream; independently executing plural streams of the iterated instruction; and recombining the independently executed plural streams to provide a single result; wherein independently executing and recombining use not more than one destination register and not more than one temporary register. In a programmable data processor including instruction interlocks and including a pipelined computation unit having a pipeline of depth p, a circuit comprises a controller constructed and arranged to detect an iterative computation in an incoming instruction stream.

6. 发明授权

US08219754B2 Context instruction cache architecture for a digital signal processor 有权
标题翻译：用于数字信号处理器的上下文指令缓存架构
公开(公告)号：US08219754B2
公开(公告)日：2012-07-10
申请号：US12835319
申请日：2010-07-13
申请人： Tushar P. Ringe , Abhijit Giri
发明人： Tushar P. Ringe , Abhijit Giri
IPC分类号： G06F13/00
CPC分类号： G06F12/0888 , G06F9/381 , Y02D10/13
摘要： Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, this is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.
摘要翻译：改进的抖动感知和自配置缓存体系结构，减少高速缓存颠覆，而不增加缓存大小或降低高速缓存命中访问时间，为DSP。在一个示例实施例中，这是通过仅选择性地高速缓存具有更高复发概率的指令来大大减少高速缓存颠簸来实现的。

7. 发明授权

US08037120B2 System and method for an efficient comparison operation of multi-bit vectors in a digital logic circuit 有权
标题翻译：用于数字逻辑电路中多位向量的有效比较操作的系统和方法
公开(公告)号：US08037120B2
公开(公告)日：2011-10-11
申请号：US11566692
申请日：2006-12-05
申请人： Abhijit Giri
发明人： Abhijit Giri
IPC分类号： G06F7/50 , G06F7/00 , G06F15/00
CPC分类号： G06F7/026 , G06F7/02 , G06F7/50
摘要： An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N−1:0] and a second N-bit vector B[N−1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N−1:0] & ˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N−1:0]^˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. The difference between the first N-bit vector A[N−1:0] and the second N-bit vector B[N−1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m
摘要翻译：一种改进的技术，显着地减少了用于确定两个多位向量之间的差异是否等于给定数目或位于数字逻辑电路中的给定两个数之间的所需逻辑和计算时间。在一个示例实施例中，这通过在数字逻辑电路中接收第一N位向量A [N-1：0]和第二N位向量B [N-1：0]来实现，其中N是非 - 零正数。然后通过使用A [N-1：0]和〜B [N-1：0]进行逐位AND（A [N-1：0]＆〜B [N-1：0]）操作获得第三N比特向量 N-1：0]。此外，通过使用A [N-1：0]和〜B来执行逐位XOR（A [N-1：0] ^〜B [N-1：0]）操作来获得第四N比特向量 [N-1：0]。然后将第一N位向量A [N-1：0]和第二N位向量B [N-1：0]之间的差被声明为等于给定数或在给定的范围内数字（+ m和+ n，m

8. 发明申请

US20110010500A1 Novel Context Instruction Cache Architecture for a Digital Signal Processor 有权
标题翻译：用于数字信号处理器的新型语境指令缓存体系结构
公开(公告)号：US20110010500A1
公开(公告)日：2011-01-13
申请号：US12835319
申请日：2010-07-13
申请人： Tushar P. Ringe , Abhijit Giri
发明人： Tushar P. Ringe , Abhijit Giri
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F9/381 , Y02D10/13
摘要： Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, this is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.
摘要翻译：改进的抖动感知和自配置缓存体系结构，减少高速缓存颠覆，而不增加缓存大小或降低高速缓存命中访问时间，为DSP。在一个示例实施例中，这是通过仅选择性地高速缓存具有更高复发概率的指令来大大减少高速缓存颠簸来实现的。

9. 发明申请

US20080172529A1 NOVEL CONTEXT INSTRUCTION CACHE ARCHITECTURE FOR A DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：数字信号处理器的新的语境指令高速缓存架构
公开(公告)号：US20080172529A1
公开(公告)日：2008-07-17
申请号：US11623760
申请日：2007-01-17
申请人： Tushar Prakash Ringe , Abhijit Giri
发明人： Tushar Prakash Ringe , Abhijit Giri
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F9/381 , Y02D10/13
摘要： Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, that is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.
摘要翻译：改进的抖动感知和自配置缓存体系结构，减少高速缓存颠覆，而不增加缓存大小或降低高速缓存命中访问时间，为DSP。在一个示例性实施例中，这是通过仅选择性地高速缓存具有更高复发概率的指令来大大减少高速缓存颠簸来实现的。

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