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    • 1. 发明授权
    • Dynamic range enhancement
    • 动态范围增强
    • US08792032B2
    • 2014-07-29
    • US13267797
    • 2011-10-06
    • Adi XhakoniDavid San Segundo BelloGeorges Gielen
    • Adi XhakoniDavid San Segundo BelloGeorges Gielen
    • H04N3/14H04N5/335
    • H04N5/2353H04N5/2355H04N5/3535H04N5/355H04N5/35554H04N5/3559
    • A method of increasing dynamic range of pixels in an imaging sensor is disclosed. In one aspect, two image captures are performed, one at a first short integration time and one at a second optimum integration time. An electrical value obtained from a pixel or group of pixels at the first short integration time is used to predict the second integration time using a comparison with a set of reference values. The reference values relate to a saturation electrical value for each pixel or group of pixels to predict the second integration time. The first short integration time is determined as a fractional multiple of the saturation electrical value. The second integration times are such that there is no saturation of the pixel or group of pixels. Adjustments can be made to the reference values to allow for offset immunity and variability in light levels during the second integration time.
    • 公开了增加成像传感器中像素的动态范围的方法。 在一个方面,执行两个图像捕获,一个在第一短积分时间,一个在第二最佳积分时间。 使用在第一短积分时间从像素或像素组获得的电值,以使用与一组参考值进行比较来预测第二积分时间。 参考值涉及每个像素或一组像素的饱和电值以预测第二积分时间。 第一个短积分时间被确定为饱和电值的分数倍。 第二积分时间使得像素或像素组没有饱和。 可以对参考值进行调整,以允许在第二积分时间期间的光水平的偏移抗扰度和变化性。
    • 2. 发明申请
    • DYNAMIC RANGE ENHANCEMENT
    • 动态范围增强
    • US20120086840A1
    • 2012-04-12
    • US13267797
    • 2011-10-06
    • Adi XhakoniDavid San Segundo BelloGeorges Gielen
    • Adi XhakoniDavid San Segundo BelloGeorges Gielen
    • H04N5/335
    • H04N5/2353H04N5/2355H04N5/3535H04N5/355H04N5/35554H04N5/3559
    • A method of increasing dynamic range of pixels in an imaging sensor is disclosed. In one aspect, two image captures are performed, one at a first short integration time and one at a second optimum integration time. An electrical value obtained from a pixel or group of pixels at the first short integration time is used to predict the second integration time using a comparison with a set of reference values. The reference values relate to a saturation electrical value for each pixel or group of pixels to predict the second integration time. The first short integration time is determined as a fractional multiple of the saturation electrical value. The second integration times are such that there is no saturation of the pixel or group of pixels. Adjustments can be made to the reference values to allow for offset immunity and variability in light levels during the second integration time.
    • 公开了增加成像传感器中像素的动态范围的方法。 在一个方面,执行两个图像捕获,一个在第一短积分时间,一个在第二最佳积分时间。 使用在第一短积分时间从像素或像素组获得的电值,以使用与一组参考值进行比较来预测第二积分时间。 参考值涉及每个像素或一组像素的饱和电值以预测第二积分时间。 第一个短积分时间被确定为饱和电值的分数倍。 第二积分时间使得像素或像素组没有饱和。 可以对参考值进行调整,以允许在第二积分时间期间的光水平的偏移抗扰度和变化性。
    • 6. 发明授权
    • Power output stage
    • 功率输出级
    • US07342448B2
    • 2008-03-11
    • US11477576
    • 2006-06-29
    • Benno MuhlbacherJoachim GratzEvelyne KrickiThomas PötscherMayk RoehrichDavid San Segundo BelloAndreas Weisbauer
    • Benno MuhlbacherJoachim GratzEvelyne KrickiThomas PötscherMayk RoehrichDavid San Segundo BelloAndreas Weisbauer
    • H03F3/217
    • H03F3/217
    • A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching transistor with a controllable path and a control terminal. A switched output signal between the controllable paths of the limiting and complementary limiting transistors can be taped off, the controllable paths of the limiting and the complementary limiting transistors are connected together and are connected to a first and a second supply terminal via the controllable paths of the switching and complementary switching transistors, and the switching and the complementary switching transistors have a lower electrical strength than the limiting and complementary limiting transistors. The output stage further comprises a level matching device for generating control signals in response to an input switching signal. The matching device is connected to the supply voltage and the control signals are fed to the control terminals.
    • 用于切换电源电压的D类功率输出级包括具有可控路径的限制晶体管和控制端子,具有可控路径的互补限制晶体管和控制端子,具有可控路径的开关晶体管和控制端子,以及 具有可控路径和控制端的互补开关晶体管。 限流和互补限制晶体管的可控路径之间的切换输出信号可以被分离,限制和互补限制晶体管的可控路径连接在一起,并且经由可控路径的可控路径连接到第一和第二供电端子 开关和互补开关晶体管,以及开关和互补开关晶体管具有比限制和互补限制晶体管更低的电气强度。 输出级还包括用于响应于输入切换信号产生控制信号的电平匹配装置。 匹配装置连接到电源电压,控制信号馈送到控制端。
    • 8. 发明申请
    • Power output stage
    • 功率输出级
    • US20070001735A1
    • 2007-01-04
    • US11477576
    • 2006-06-29
    • Benno MuhlbacherAchim GratzEvelyne KricklThomas PotscherMayk RoehrichDavid San Segundo BelloAndreas Weisbauer
    • Benno MuhlbacherAchim GratzEvelyne KricklThomas PotscherMayk RoehrichDavid San Segundo BelloAndreas Weisbauer
    • H03K3/00
    • H03F3/217
    • A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching transistor with a controllable path and a control terminal. A switched output signal between the controllable paths of the limiting and complementary limiting transistors can be taped off, the controllable paths of the limiting and the complementary limiting transistors are connected together and are connected to a first and a second supply terminal via the controllable paths of the switching and complementary switching transistors, and the switching and the complementary switching transistors have a lower electrical strength than the limiting and complementary limiting transistors. The output stage further comprises a level matching device for generating control signals in response to an input switching signal. The matching device is connected to the supply voltage and the control signals are fed to the control terminals.
    • 用于切换电源电压的D类功率输出级包括具有可控路径的限制晶体管和控制端子,具有可控路径的互补限制晶体管和控制端子,具有可控路径的开关晶体管和控制端子,以及 具有可控路径和控制端的互补开关晶体管。 限流和互补限制晶体管的可控路径之间的切换输出信号可以被分离,限制和互补限制晶体管的可控路径连接在一起,并经由可控路径的可控路径连接到第一和第二供电端子 开关和互补开关晶体管,以及开关和互补开关晶体管具有比限制和互补限制晶体管更低的电气强度。 输出级还包括用于响应于输入切换信号产生控制信号的电平匹配装置。 匹配装置连接到电源电压,控制信号馈送到控制端。