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1. 发明授权

US11640444B2 Device and method for accelerating matrix multiply operations 有权
公开(公告)号：US11640444B2
公开(公告)日：2023-05-02
申请号：US17208526
申请日：2021-03-22
申请人： Advanced Micro Devices, Inc.
发明人： Shaizeen Aga , Nuwan Jayasena , Allen H. Rush , Michael Ignatowski
IPC分类号： G06F17/16 , G06F7/53 , G06F15/80
摘要： A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.

2. 发明申请

US20160231933A1 MEMORY PAGE ACCESS DETECTION 有权
标题翻译：存储页访问检测
公开(公告)号：US20160231933A1
公开(公告)日：2016-08-11
申请号：US14616058
申请日：2015-02-06
申请人： Advanced Micro Devices, Inc.
发明人： Gabriel H. Loh , David A. Roberts , Mitesh R. Meswani , Mark R. Nutter , John R. Slice , Prashant Nair , Michael Ignatowski
IPC分类号： G06F3/06 , G06F12/10 , G06F12/08
CPC分类号： G06F3/0604 , G06F3/0653 , G06F3/0673 , G06F12/0893 , G06F12/1027 , G06F12/1045 , G06F2212/60 , G06F2212/68
摘要： A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.
摘要翻译：处理器维护对每个存储器页面的访问次数。当对存储器页的访问超过该存储器页的阈值量时，处理器设置页面的指示符。基于内存页面的指示器，处理器在处理器的存储器层次结构的一个或多个级别管理数据。

3. 发明申请

US20140181458A1 DIE-STACKED MEMORY DEVICE PROVIDING DATA TRANSLATION 有权
标题翻译：提供数据翻译的DIE堆叠存储器件
公开(公告)号：US20140181458A1
公开(公告)日：2014-06-26
申请号：US13726143
申请日：2012-12-23
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
摘要翻译：芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。

4. 发明授权

US11604754B2 Method and apparatus of integrating memory stacks 有权
公开(公告)号：US11604754B2
公开(公告)日：2023-03-14
申请号：US15605291
申请日：2017-05-25
申请人： Advanced Micro Devices, Inc.
发明人： Dmitri Yudanov , Michael Ignatowski
IPC分类号： G06F13/16 , G06F13/40 , G11C29/02 , G11C29/30 , G11C29/44 , G11C5/02 , G11C5/06 , G11C5/14 , G11C7/06 , G11C7/10
摘要： A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.

5. 发明申请

US20220365975A1 FLEXIBLE, SCALABLE GRAPH-PROCESSING ACCELERATOR 有权
公开(公告)号：US20220365975A1
公开(公告)日：2022-11-17
申请号：US17564413
申请日：2021-12-29
申请人： Advanced Micro Devices, Inc.
发明人： Ganesh Dasika , Michael Ignatowski , Michael J. Schulte , Gabriel H. Loh , Valentina Salapura , Angela Beth Dalton
IPC分类号： G06F16/901 , G06F15/80
摘要： An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

6. 发明申请

US20210165721A1 METHOD FOR A RELIABILITY, AVAILABILITY, AND SERVICEABILITY-CONSCIOUS HUGE PAGE SUPPORT 有权
公开(公告)号：US20210165721A1
公开(公告)日：2021-06-03
申请号：US16700993
申请日：2019-12-02
申请人： Advanced Micro Devices, Inc.
发明人： Sergey Blagodurov , Michael Ignatowski , Vilas Sridharan
IPC分类号： G06F11/20
摘要： A method includes reserving memory capacity in a first memory device as patch memory region for backing faulted memory, receiving a memory error indication indicating an uncorrectable error in a faulted segment in a second memory device and, in response to the memory error indication, associating in a remapping table the faulted segment with a patch segment in the patch memory region. The faulted segment is smaller than a memory page size of the second memory device. The method also includes, in response to receiving a memory access request directed to the faulted memory segment, servicing the memory access request from the patch segment by querying the remapping table to determine a patch segment address corresponding to a requested memory address, where the patch segment address identifies the location of the patch segment, and based on the patch segment address, performing the requested memory access at the patch segment.

7. 发明申请

US20170147228A1 COMPUTATION ALONG A DATAPATH BETWEEN MEMORY BLOCKS 审中-公开
公开(公告)号：US20170147228A1
公开(公告)日：2017-05-25
申请号：US14952517
申请日：2015-11-25
申请人： Advanced Micro Devices, Inc.
发明人： Dmitri Yudanov , Sergey Blagodurov , David A. Roberts , Mitesh R. Meswani , Nuwan Jayasena , Michael Ignatowski
IPC分类号： G06F3/06
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0888 , G06F13/16 , G06F13/4022 , G06F15/7821 , G06F2212/1024
摘要： A plurality of memory blocks are connected to a computation-enabled switch that provides data paths between the plurality of memory blocks. The computation-enabled switch performs one or more computations on data stored in one or more of the plurality of memory blocks during transfer of the data along one or more of the data paths between the plurality of memory blocks.

8. 发明申请

US20160155491A1 MEMORY PERSISTENCE MANAGEMENT CONTROL 审中-公开
标题翻译：记忆持续管理控制
公开(公告)号：US20160155491A1
公开(公告)日：2016-06-02
申请号：US14555639
申请日：2014-11-27
申请人： Advanced Micro Devices, Inc.
发明人： David A. Roberts , Michael Ignatowski
IPC分类号： G11C11/406
CPC分类号： G11C11/40607 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C2211/4067 , G11C2211/4068
摘要： A memory retention controller may include a data structure configured to store a memory refresh interval corresponding to a memory region in a memory subsystem and control logic coupled with the data structure. The control logic is configured to perform a first refresh of the memory region prior to a power off transition of a host processor coupled with the memory subsystem, and to perform a second refresh of the memory region after the power off transition of the host processor, based on the memory refresh interval corresponding to the memory region, and in response to an elapsed time since the first refresh of the memory region.
摘要翻译：存储器保持控制器可以包括被配置为存储对应于存储器子系统中的存储器区域的存储器刷新间隔和与数据结构耦合的控制逻辑的数据结构。控制逻辑被配置为在与存储器子系统耦合的主处理器的断电转换之前执行存储器区域的第一刷新，并且在主处理器的电源转换之后执行存储器区域的第二次刷新，基于与存储器区域相对应的存储器刷新间隔，并且响应于自存储区域的第一次刷新以来的经过时间。

9. 发明申请

US20140181483A1 Computation Memory Operations in a Logic Layer of a Stacked Memory 有权
标题翻译：堆叠存储器逻辑层中的计算存储器操作
公开(公告)号：US20140181483A1
公开(公告)日：2014-06-26
申请号：US13724506
申请日：2012-12-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： James M. O'CONNOR , Nuwan S. Jayasena , Gabriel H. Loh , Michael Ignatowski , Michael J. Schulte
IPC分类号： G06F9/30
CPC分类号： G06F15/7821 , Y02D10/12 , Y02D10/13
摘要： Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.
摘要翻译：除了一层或多层DRAM（或其他存储器技术）之外，一些堆叠堆叠的存储器将包含逻辑层。该逻辑层可以是与存储器管芯堆叠相关联的硅插入器上的离散逻辑管芯或逻辑。额外的电路/功能被放置在逻辑层上以实现执行各种计算操作的功能。通过避免通过接口向主机处理器传输数据，执行本地在存储器件附近的操作将允许提高性能和/或功率效率将需要该功能。

10. 发明申请

US20140181427A1 Compound Memory Operations in a Logic Layer of a Stacked Memory 审中-公开
标题翻译：堆叠存储器的逻辑层中的复合存储器操作
公开(公告)号：US20140181427A1
公开(公告)日：2014-06-26
申请号：US13724338
申请日：2012-12-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Nuwan S. JAYASENA , James M. O'Connor , Gabriel H. Loh , Michael J. Schulte , Bradford M. Beckmann , Michael Ignatowski
IPC分类号： G06F12/00
CPC分类号： G06F9/3004 , G06F9/3455 , G06F15/7821
摘要： Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various data movement and address calculation operations. This functionality would allow compound memory operations—a single request communicated to the memory that characterizes the accesses and movement of many data items. This eliminates the performance and power overheads associated with communicating address and control information on a fine-grain, per-data-item basis from a host processor (or other device) to the memory. This approach also provides better visibility of macro-level memory access patterns to the memory system and may enable additional optimizations in scheduling memory accesses.
摘要翻译：除了一层或多层DRAM（或其他存储器技术）之外，一些堆叠堆叠的存储器将包含逻辑层。该逻辑层可以是与存储器管芯堆叠相关联的硅插入器上的离散逻辑管芯或逻辑。额外的电路/功能被放置在逻辑层上以实现执行各种数据移动和地址计算操作的功能。该功能将允许复合存储器操作 - 传达到存储器的单个请求，其表征许多数据项的访问和移动。这消除了与从主处理器（或其他设备）到存储器的以细粒度，每数据项为基础传送地址和控制信息相关联的性能和功耗开销。这种方法还提供了对存储器系统的宏级存储器访问模式的更好的可见性，并且可以在调度存储器访问中实现附加优化。

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