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1. 发明申请

US20190121724A1 APPARATUSES AND METHODS FOR MEMORY DEVICE AS A STORE FOR PROGRAM INSTRUCTIONS 审中-公开
公开(公告)号：US20190121724A1
公开(公告)日：2019-04-25
申请号：US16224498
申请日：2018-12-18
申请人： Micron Technology, Inc.
发明人： Jason T. Zawodny , Kyle B. Wheeler , Richard C. Murphy
IPC分类号： G06F12/02 , G06F15/78 , G11C11/408 , G11C7/06 , G06F12/0888 , G11C11/4096 , G11C7/10
CPC分类号： G06F12/0238 , G06F12/0888 , G06F15/7821 , G06F2212/202 , G06F2212/603 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1036 , G11C8/12 , G11C11/4087 , G11C11/4096
摘要： Apparatuses and methods related to a memory device as the store to program instructions are described. An apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry, is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

2. 发明申请

US20190034097A1 COORDINATED NEAR-FAR MEMORY CONTROLLER FOR PROCESS-IN-HBM 审中-公开
公开(公告)号：US20190034097A1
公开(公告)日：2019-01-31
申请号：US15723014
申请日：2017-10-02
申请人： Samsung Electronics Co., Ltd.
发明人： Mu-Tien Chang , Dimin Niu , Hongzhong Zheng
IPC分类号： G06F3/06
CPC分类号： G06F3/0617 , G06F3/0653 , G06F3/0659 , G06F12/0292 , G06F13/16 , G06F15/7821 , G06F2212/1016
摘要： A method of coordinating memory commands in a high-bandwidth memory HBM+ system, the method including sending a host memory controller command from a host memory controller to a memory, receiving the host memory controller command at a coordinating memory controller, forwarding the host memory controller command from the coordinating memory controller to the memory, and scheduling, by the coordinating memory controller, a coordinating memory controller command based on the host memory controller command.

3. 发明申请

US20180365020A1 GENERATING AND EXECUTING A CONTROL FLOW 审中-公开
公开(公告)号：US20180365020A1
公开(公告)日：2018-12-20
申请号：US16112577
申请日：2018-08-24
申请人： Micron Technology, Inc.
发明人： Kyle B. Wheeler , Richard C. Murphy , Troy A. Manning , Dean A. Klein
IPC分类号： G06F9/38 , G11C7/06 , G11C7/10 , G11C11/408 , G11C11/4096 , G06F15/78
CPC分类号： G06F9/3877 , G06F15/7821 , G11C7/06 , G11C7/065 , G11C7/1006 , G11C7/1036 , G11C11/4087 , G11C11/4096
摘要： Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

4. 发明授权

US09858242B2 Memory controller for a network on a chip device 有权
公开(公告)号：US09858242B2
公开(公告)日：2018-01-02
申请号：US15369954
申请日：2016-12-06
申请人： KnuEdge Incorporated
发明人： Douglas A. Palmer , Ramon Zuniga
IPC分类号： G06F13/00 , G06F15/78 , G06F13/16 , H04L12/717 , G06F13/28 , G06F13/42 , H04L12/741 , H04L12/715 , H04L12/933
CPC分类号： G06F15/7825 , G06F13/1657 , G06F13/1694 , G06F13/28 , G06F13/4234 , G06F15/7821 , H04L45/42 , H04L45/46 , H04L45/74 , H04L49/109
摘要： Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. The memory controller may comprise a first interface to be coupled to a router. The first interface may be configured to transmit and receive packets. Each packet may comprise a header that may contain a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol. The memory controller may further comprise a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory and a controller core coupled to the first interface. The controller core may be configured to decode a packet received at the first interface and perform an operation specified in the received packet.

5. 发明申请

US20170300433A1 TRANS-FABRIC INSTRUCTION SET FOR A COMMUNICATION FABRIC 审中-公开
公开(公告)号：US20170300433A1
公开(公告)日：2017-10-19
申请号：US15518195
申请日：2014-10-29
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： Melvin K. Benedict , Michael R. Krause , Mitchel E. Wright
IPC分类号： G06F13/16 , G06F15/78 , H04L12/911
CPC分类号： G06F13/1668 , G06F13/1694 , G06F15/7821 , H04L47/70
摘要： A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.

6. 发明申请

US20170060588A1 COMPUTING SYSTEM AND METHOD FOR PROCESSING OPERATIONS THEREOF 审中-公开
标题翻译：计算机系统及其处理方法
公开(公告)号：US20170060588A1
公开(公告)日：2017-03-02
申请号：US15067494
申请日：2016-03-11
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Yoonseo CHOI
IPC分类号： G06F9/30
CPC分类号： G06F9/3881 , G06F15/7821 , G06F15/80 , Y02D10/12 , Y02D10/13
摘要： A computing system includes a host processor configured to process operations and a memory configured to include an internal processor and store host instructions to be processed by the host processor. The host processor offloads processing of a predetermined operation to the internal processor. The internal processor possibly provides specialized hardware designed to process the operation efficiently, improving the efficiency and performance of the computing system.
摘要翻译：计算系统包括被配置为处理操作的主机处理器和被配置为包括内部处理器并存储要由主处理器处理的主机指令的存储器。主处理器将预定操作的处理卸载到内部处理器。内部处理器可能提供专门用于高效处理操作的硬件，提高计算系统的效率和性能。

7. 发明申请

US20160379686A1 SERVER SYSTEMS WITH HARDWARE ACCELERATORS INCLUDING STACKED MEMORY 审中-公开
标题翻译：带有硬件加速器的服务器系统，包括堆叠存储器
公开(公告)号：US20160379686A1
公开(公告)日：2016-12-29
申请号：US14754295
申请日：2015-06-29
申请人： Microsoft Technology Licensing, LLC
发明人： Douglas C. Burger , Andrew R. Putnam , Eric Chung
IPC分类号： G11C5/02 , G06F3/06
CPC分类号： G11C5/02 , G06F3/0604 , G06F3/0631 , G06F3/0683 , G06F15/7821 , G06N3/063 , G06N3/084 , G06N5/025 , Y02D10/12 , Y02D10/13
摘要： A server unit component is provided that includes a host component including a CPU, and an acceleration component coupled to the host component. The acceleration component includes an acceleration component die and a memory stack. The acceleration component die and the memory stack are disposed in an integrated circuit package. The memory stack has a memory bandwidth greater than about 50 GB/sec and a power efficiency of greater than about 20 MB/sec/mW.
摘要翻译：提供了一种服务器单元组件，其包括包括CPU的主机组件和耦合到主机组件的加速组件。加速度分量包括加速度分量模具和存储器堆叠。加速度分量芯片和存储器堆叠被布置在集成电路封装中。存储器堆栈具有大于约50GB /秒的存储器带宽和大于约20MB / sec / mW的功率效率。

8. 发明申请

US20160077577A1 MEMORY AND PROCESSOR HIERARCHY TO IMPROVE POWER EFFICIENCY 有权
标题翻译：记忆和处理器分层提高功率效率
公开(公告)号：US20160077577A1
公开(公告)日：2016-03-17
申请号：US14855803
申请日：2015-09-16
申请人： International Business Machines Corporation
发明人： Jan VAN LUNTEREN , Heiner GIEFERS
IPC分类号： G06F1/32 , G06F3/06 , G06F9/30
CPC分类号： G06F12/02 , G06F1/3275 , G06F9/265 , G06F9/30007 , G06F9/3004 , G06F9/3824 , G06F9/3836 , G06F9/3889 , G06F15/7821 , G06F15/80 , Y02D10/13 , Y02D10/14
摘要： A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.
摘要翻译：计算存储器包括与存储器系统耦合的执行单元和访问处理器，其中执行单元和访问处理器是逻辑上分离的单元。执行单元用于处理操作数数据。访问处理器用于向执行单元提供操作数数据和配置数据。访问处理器从存储器系统读取操作数据，并将操作数数据发送到执行单元。执行单元根据所提供的配置数据执行操作数数据。访问处理器包括关于所提供的配置的执行单元的操作的执行时间的信息。在将至少一个操作数数据和配置数据发送到执行单元时，接入处理器基于关于执行时间的信息来保留用于将执行单元提供的执行单元结果写入存储器系统中的选定位置的时隙。

9. 发明申请

US20160041785A1 CONTROL OF PAGE ACCESS IN MEMORY 有权
公开(公告)号：US20160041785A1
公开(公告)日：2016-02-11
申请号：US14918364
申请日：2015-10-20
申请人： Micron Technology, Inc.
发明人： Robert Walker
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/061 , G06F3/0644 , G06F3/0688 , G06F3/0689 , G06F12/00 , G06F12/0215 , G06F12/06 , G06F12/14 , G06F13/00 , G06F13/14 , G06F13/16 , G06F13/161 , G06F13/1615 , G06F13/1668 , G06F13/4243 , G06F15/7821 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

10. 发明授权

US09026719B2 Intelligent monitoring for computation in memory 有权
标题翻译：内存计算智能监控
公开(公告)号：US09026719B2
公开(公告)日：2015-05-05
申请号：US13678430
申请日：2012-11-15
申请人： Elwha LLC
发明人： Roderick A. Hyde , Nicholas F. Pasch , Clarence T. Tegreene
IPC分类号： G06F12/02 , G06F11/34 , G11C29/04 , G11C29/44 , G06F15/78
CPC分类号： G06F12/0246 , G06F11/3037 , G06F11/3055 , G06F11/34 , G06F11/3433 , G06F11/3466 , G06F15/7821 , G11C2029/0409 , G11C2029/4402
摘要： A memory device can include a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to selectively distribute functionality across the non-volatile memory array.
摘要翻译：存储器装置可以包括与非易失性存储器阵列集成并分布在非易失性存储器阵列上的非易失性存储器阵列和控制逻辑。控制逻辑可以用于选择性地跨越非易失性存储器阵列分配功能。

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