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1. 发明授权

US09372803B2 Method and system for shutting down active core based caches 有权
标题翻译：关闭基于活动核心的缓存的方法和系统
公开(公告)号：US09372803B2
公开(公告)日：2016-06-21
申请号：US13722808
申请日：2012-12-20
申请人： Advanced Micro Devices, Inc.
发明人： Srilatha Manne , Michael Schulte , Lloyd Bircher , Madhu Saravana Sibi Govindan , Yasuko Eckert
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0806 , G06F2212/1028 , Y02D10/13
摘要： A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.
摘要翻译：提出了一种系统和方法。一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为处于修改状态。通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度，与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

2. 发明授权

US09367455B2 Using predictions for store-to-load forwarding 有权
标题翻译：使用商店到装载转发的预测
公开(公告)号：US09367455B2
公开(公告)日：2016-06-14
申请号：US14018562
申请日：2013-09-05
申请人： Advanced Micro Devices, Inc.
发明人： Yasuko Eckert , Lena E. Olson , Srilatha Manne , James M. O'Connor
IPC分类号： G06F9/30 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0802 , G06F9/3834 , G06F9/3838 , G06F12/0848 , G06F12/0862 , G06F12/0864 , G06F12/0875 , G06F12/123 , G06F2212/1016 , G06F2212/451 , G06F2212/502 , G06F2212/6022 , G06F2212/6032 , Y02D10/13
摘要： The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.
摘要翻译：所描述的实施例包括使用对存储到负载转发的预测的核心。在所描述的实施例中，核心包括加载存储单元，存储缓冲器和预测机制。在运行期间，预测机制产生一个预测，即使用从存储缓冲器转发的数据来满足负载，因为负载从栈中的存储器位置加载数据。基于该预测，加载存储单元首先向存储缓冲器发送对数据的请求，以尝试使用从存储缓冲器转发的数据来满足负载。如果从存储缓冲区返回数据，则使用该数据来满足负载。然而，如果使用从存储缓冲器转发的数据来满足负载的尝试不成功，则加载存储单元然后分别向缓存发送用于满足负载的数据请求。

3. 发明授权

US09251069B2 Mechanisms to bound the presence of cache blocks with specific properties in caches 有权
标题翻译：限制缓存中具有特定属性的高速缓存块的存在的机制
公开(公告)号：US09251069B2
公开(公告)日：2016-02-02
申请号：US14055869
申请日：2013-10-16
申请人： Advanced Micro Devices, Inc.
发明人： Yasuko Eckert , Gabriel H. Loh , Mauricio Breternitz , James M. O'Connor , Srilatha Manne , Nuwan S. Jayasena , Mithuna S. Thottethodi
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F1/3225 , G06F1/3275 , G06F12/0848 , G06F12/0888 , G06F12/0897 , Y02D10/13 , Y02D10/14
摘要： A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.
摘要翻译：一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。计算系统包括高速缓存阵列和对应的高速缓存控制器。高速缓存阵列包括多个存储体，其中第一存储体断电。作为响应，向第二存储体写入请求以指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。高速缓存控制器将这些数据写入较低级别的内存。

4. 发明申请

US20140181537A1 GUARDBAND REDUCTION FOR MULTI-CORE DATA PROCESSOR 有权
标题翻译：多核数据处理器的保护减少
公开(公告)号：US20140181537A1
公开(公告)日：2014-06-26
申请号：US13724271
申请日：2012-12-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Srilatha Manne , Rajagopalan Desikan , Sanjay Pant , Youngtaek Kim
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.
摘要翻译：多核数据处理器包括多个数据处理器内核和电源控制器。每个数据处理器内核具有用于接收时钟信号的第一输入端，用于接收电源电压的第二输入端和用于提供空闲信号的输出端。功率控制器耦合到每个数据处理器核心，用于向每个数据处理器核提供时钟信号和电源电压。功率控制器根据从数据处理器核心接收到的空闲信号的数量，向时钟信号和电源电压提供至少一个数据处理器核心中的一个。

5. 发明申请

US20140181413A1 METHOD AND SYSTEM FOR SHUTTING DOWN ACTIVE CORE BASED CACHES 有权
标题翻译：用于切换基于活动核心的快照的方法和系统
公开(公告)号：US20140181413A1
公开(公告)日：2014-06-26
申请号：US13722808
申请日：2012-12-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Srilatha Manne , Michael Schulte , Lloyd Bircher , Madhu Saravana Sibi Govindan , Yasuko Eckert
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0806 , G06F2212/1028 , Y02D10/13
摘要： A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.
摘要翻译：提出了一种系统和方法。一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为处于修改状态。通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度，与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

6. 发明申请

US20140143498A1 METHODS AND APPARATUS FOR FILTERING STACK DATA WITHIN A CACHE MEMORY HIERARCHY 审中-公开
标题翻译：用于在高速缓存存储器层次中过滤堆叠数据的方法和装置
公开(公告)号：US20140143498A1
公开(公告)日：2014-05-22
申请号：US13945620
申请日：2013-07-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Lena E. Olson , Yasuko Eckert , Vilas K. Sridharan , James M. O'Connor , Mark D. Hill , Srilatha Manne
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/08 , G06F12/0804 , G06F12/0811 , G06F12/0815 , G06F12/0848 , G06F12/0862 , G06F12/0864 , G06F12/0875 , G06F12/1036 , G06F12/123 , G06F2212/1016 , G06F2212/1028 , G06F2212/451 , G06F2212/6032 , G06F2212/683 , G06F2212/684 , Y02B60/1225 , Y02D10/13
摘要： A method of storing stack data in a cache hierarchy is provided. The cache hierarchy comprises a data cache and a stack filter cache. Responsive to a request to access a stack data block, the method stores the stack data block in the stack filter cache, wherein the stack filter cache is configured to store any requested stack data block.
摘要翻译：提供了将堆栈数据存储在高速缓存层级中的方法。缓存层级包括数据高速缓存和堆栈过滤器高速缓存。响应于访问堆栈数据块的请求，该方法将堆栈数据块存储在堆栈过滤器高速缓存中，其中堆叠过滤器高速缓存被配置为存储任何所请求的栈数据块。

7. 发明授权

US10025361B2 Power management across heterogeneous processing units 有权
公开(公告)号：US10025361B2
公开(公告)日：2018-07-17
申请号：US14297208
申请日：2014-06-05
申请人： Advanced Micro Devices, Inc.
发明人： Indrani Paul , Vignesh Trichy Ravi , Manish Arora , Srilatha Manne
IPC分类号： G06F1/00 , G06F1/20 , G06F1/32 , G06F11/30 , G06F9/50 , G06F11/34
摘要： A method includes controlling active frequency states of a plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. A processor includes a plurality of heterogeneous processing units and a performance controller to control active frequency states of the plurality of heterogeneous processing units based on frequency sensitivity metrics indicating performance coupling between different types of processing units in the plurality of heterogeneous processing units. The active frequency state of a first type of processing unit in the plurality of heterogeneous processing units is controlled based on a first activity metric associated with a first type of processing unit and a second activity metric associated with a second type of processing unit.

8. 发明授权

US09946319B2 Setting power-state limits based on performance coupling and thermal coupling between entities in a computing device 有权
公开(公告)号：US09946319B2
公开(公告)日：2018-04-17
申请号：US14059384
申请日：2013-10-21
申请人： Advanced Micro Devices, Inc.
发明人： Indrani Paul , Manish Arora , Srilatha Manne , William L. Bircher
IPC分类号： G06F1/32 , G06F1/20
CPC分类号： G06F1/3206 , G06F1/206
摘要： The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

9. 发明授权

US09710392B2 Virtual memory mapping for improved DRAM page locality 有权
公开(公告)号：US09710392B2
公开(公告)日：2017-07-18
申请号：US14460550
申请日：2014-08-15
申请人： Advanced Micro Devices, Inc.
发明人： Syed Ali Jafri , Yasuko Eckert , Srilatha Manne , Mithuna S Thottethodi
IPC分类号： G06F12/10 , G06F12/1009
CPC分类号： G06F12/1009 , G06F2212/1024 , G06F2212/654 , G06F2212/655 , G06F2212/656
摘要： Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.

10. 发明授权

US09360918B2 Power control for multi-core data processor 有权
标题翻译：多核数据处理器的电源控制
公开(公告)号：US09360918B2
公开(公告)日：2016-06-07
申请号：US13724133
申请日：2012-12-21
申请人： Advanced Micro Devices, Inc.
发明人： Srilatha Manne , Sanjay Pant , Youngtaek Kim , Michael J. Schulte
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , Y02D10/152
摘要： A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.
摘要翻译：多核数据处理器包括多个数据处理器核心和一个电路。多个数据处理器核心各自包括具有用于接收空闲信号的第一输入的功率状态控制器，用于接收释放信号的第二输入，用于接收控制信号的第三输入和用于提供当前功率状态的输出。响应于空闲信号，电源状态控制器使相应的数据处理器核进入空闲状态。响应于释放信号，功率状态控制器根据控制信号将当前功率状态从空闲状态改变到活动状态。电路耦合到多个数据处理器核心中的每一个，以响应于多个数据处理器核心中的当前功率状态来提供控制信号。

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