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1. 发明授权

US09372803B2 Method and system for shutting down active core based caches 有权
标题翻译：关闭基于活动核心的缓存的方法和系统
公开(公告)号：US09372803B2
公开(公告)日：2016-06-21
申请号：US13722808
申请日：2012-12-20
申请人： Advanced Micro Devices, Inc.
发明人： Srilatha Manne , Michael Schulte , Lloyd Bircher , Madhu Saravana Sibi Govindan , Yasuko Eckert
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0806 , G06F2212/1028 , Y02D10/13
摘要： A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.
摘要翻译：提出了一种系统和方法。一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为处于修改状态。通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度，与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

2. 发明申请

US20140181413A1 METHOD AND SYSTEM FOR SHUTTING DOWN ACTIVE CORE BASED CACHES 有权
标题翻译：用于切换基于活动核心的快照的方法和系统
公开(公告)号：US20140181413A1
公开(公告)日：2014-06-26
申请号：US13722808
申请日：2012-12-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Srilatha Manne , Michael Schulte , Lloyd Bircher , Madhu Saravana Sibi Govindan , Yasuko Eckert
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0806 , G06F2212/1028 , Y02D10/13
摘要： A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.
摘要翻译：提出了一种系统和方法。一些实施例包括处理单元，耦合到处理单元的至少一个存储器以及耦合到处理单元并被分成一系列块的至少一个高速缓存，其中该系列高速缓存块中的至少一个包括被识别为处于修改状态。通过基于回写策略将数据写入至少一个存储器来刷新修改的状态数据，并且策略的侵略性基于至少一个因素，包括空闲核心数量，最后一个高速缓存刷新的接近度，与数据相关联的线程的活动，以及哪些核心是空闲的，以及空闲核心是否与数据相关联。

3. 发明授权

US09213585B2 Controlling sprinting for thermal capacity boosted systems 有权
标题翻译：控制用于热容量提升系统的冲刺
公开(公告)号：US09213585B2
公开(公告)日：2015-12-15
申请号：US13925269
申请日：2013-06-24
申请人： Advanced Micro Devices, Inc.
发明人： Manish Arora , Nuwan Jayasena , Michael Schulte
IPC分类号： G06F9/46 , G06F15/00 , G06F9/50 , G06F1/20 , G06F1/32 , G06F9/30
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/324 , G06F9/30189 , G06F9/5011 , Y02D10/126 , Y02D10/22
摘要： A method and apparatus are described for performing sprinting in a processor. An analyzer in the processor may monitor thermal capacity remaining in the processor while not sprinting. When the remaining thermal capacity is sufficient to support sprinting, the analyzer may perform sprinting of a new workload when a benefit derived by sprinting the new workload exceeds a threshold and does not cause the remaining thermal capacity in the processor to be exhausted. The analyzer may perform sprinting of the new workload in accordance with sprinting parameters determined for the new workload. The analyzer may continue to monitor the remaining thermal capacity while not sprinting when the benefit derived by sprinting the new workload does not exceed the threshold.
摘要翻译：描述了用于在处理器中执行冲刺的方法和装置。处理器中的分析仪可以监控处理器中剩余的热量，而不会冲击。当剩余的热容量足以支持冲刺时，当通过冲击新工作负载导致的好处超过阈值并且不会导致处理器中的剩余热容量被耗尽时，分析器可以执行新工作负载的冲刺。分析器可以根据为新工作负载确定的冲刺参数执行新工作负载的冲刺。当通过冲击新工作负载得到的好处不超过阈值时，分析仪可以继续监视剩余热容量而不冲刺。

4. 发明申请

US20150067356A1 POWER MANAGER FOR MULTI-THREADED DATA PROCESSOR 审中-公开
标题翻译：多线程数据处理器的电源管理器
公开(公告)号：US20150067356A1
公开(公告)日：2015-03-05
申请号：US14015369
申请日：2013-08-30
申请人： Advanced Micro Devices, Inc.
发明人： Vignesh Trichy Ravi , Manish Arora , William Brantley , Srilatha Manne , Indrani Paul , Michael Schulte
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： A data processing system includes a plurality of processor resources, a manager, and a power distributor. Each of the plurality of data processor cores is operable at a selected one of a plurality of performance states. The manager assigns each of a plurality of program elements to one of the plurality of processor resources, and synchronizing the program elements using barriers. The power distributor is coupled to the manager and to the plurality of processor resources, and assigns a performance state to each of the plurality of processor resources within an overall power budget, and in response to detecting that a program element assigned to a first processor resource is at a barrier, increases the performance state of a second processor resource that is not at the barrier within the overall power budget.
摘要翻译：数据处理系统包括多个处理器资源，管理器和功率分配器。多个数据处理器核心中的每一个可操作在多个执行状态中的选定的一个。管理器将多个程序元素中的每一个分配给多个处理器资源中的一个，并且使用屏障同步程序元素。功率分配器耦合到管理器和多个处理器资源，并且在总功率预算内为多个处理器资源中的每一个分配一个性能状态，并且响应于检测到分配给第一处理器资源的程序元件处于障碍之下，增加在整个功率预算范围内不处于障碍的第二处理器资源的性能状态。

5. 发明申请

US20140380329A1 CONTROLLING SPRINTING FOR THERMAL CAPACITY BOOSTED SYSTEMS 有权
标题翻译：控制用于热能增强系统的弹簧
公开(公告)号：US20140380329A1
公开(公告)日：2014-12-25
申请号：US13925269
申请日：2013-06-24
申请人： Advanced Micro Devices, Inc.
发明人： Manish Arora , Nuwan Jayasena , Michael Schulte
IPC分类号： G06F9/50
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/324 , G06F9/30189 , G06F9/5011 , Y02D10/126 , Y02D10/22
摘要： A method and apparatus are described for performing sprinting in a processor. An analyzer in the processor may monitor thermal capacity remaining in the processor while not sprinting. When the remaining thermal capacity is sufficient to support sprinting, the analyzer may perform sprinting of a new workload when a benefit derived by sprinting the new workload exceeds a threshold and does not cause the remaining thermal capacity in the processor to be exhausted. The analyzer may perform sprinting of the new workload in accordance with sprinting parameters determined for the new workload. The analyzer may continue to monitor the remaining thermal capacity while not sprinting when the benefit derived by sprinting the new workload does not exceed the threshold.
摘要翻译：描述了用于在处理器中执行冲刺的方法和装置。处理器中的分析仪可以监控处理器中剩余的热量，而不会冲击。当剩余的热容量足以支持冲刺时，当通过冲击新工作负载导致的好处超过阈值并且不会导致处理器中的剩余热容量被耗尽时，分析器可以执行新工作负载的冲刺。分析器可以根据为新工作负载确定的冲刺参数执行新工作负载的冲刺。当通过冲击新工作负载得到的好处不超过阈值时，分析仪可以继续监视剩余热容量而不冲刺。

6. 发明申请

US20140181415A1 PREFETCHING FUNCTIONALITY ON A LOGIC DIE STACKED WITH MEMORY 审中-公开
标题翻译：在与存储器堆叠的逻辑芯片上的预制功能
公开(公告)号：US20140181415A1
公开(公告)日：2014-06-26
申请号：US13723285
申请日：2012-12-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Gabriel Loh , Nuwan Jayasena , James O'Connor , Michael Schulte , Michael Ignatowski
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： Prefetching functionality on a logic die stacked with memory is described herein. A device includes a logic chip stacked with a memory chip. The logic chip includes a control block, an in-stack prefetch request handler and a memory controller. The control block receives memory requests from an external source and determines availability of the requested data in the in-stack prefetch request handler. If the data is available, the control block sends the requested data to the external source. If the data is not available, the control block obtains the requested data via the memory controller. The in-stack prefetch request handler includes a prefetch controller, a prefetcher and a prefetch buffer. The prefetcher monitors the memory requests and based on observed patterns, issues additional prefetch requests to the memory controller.
摘要翻译：本文描述了在与存储器堆叠的逻辑管芯上的预取功能。一种器件包括堆叠有存储器芯片的逻辑芯片。逻辑芯片包括控制块，堆叠预取请求处理程序和存储器控制器。控制块从外部源接收存储器请求，并确定栈内预取请求处理程序中所请求数据的可用性。如果数据可用，则控制块将所请求的数据发送到外部源。如果数据不可用，则控制块通过存储器控制器获得所请求的数据。栈内预取请求处理程序包括预取控制器，预取器和预取缓冲区。预取器监视存储器请求并基于观察到的模式，向存储器控制器发出额外的预取请求。

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