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1. 发明授权

US08443051B2 Direct memory access buffer management 有权
标题翻译：直接内存访问缓冲区管理
公开(公告)号：US08443051B2
公开(公告)日：2013-05-14
申请号：US12550005
申请日：2009-08-28
申请人： Ajoy Siddabathuni , Arvind Srinivasan , Shimon Muller
发明人： Ajoy Siddabathuni , Arvind Srinivasan , Shimon Muller
IPC分类号： G06F15/167
CPC分类号： G06F13/28
摘要： Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.
摘要翻译：公开了用于在通过网络进行数据传输的输入/输出设备（I / O设备）执行的直接存储器访问（DMA）操作期间回收缓冲器的系统和方法。在数据传输期间，I / O设备可以取消由设备驱动器提供的缓冲器，从而放弃缓冲器的所有权。放弃缓冲器所有权的I / O设备的条件可以由可能与缓冲器相关联的距离向量来提供。距离向量可以指定缓冲区和I / O设备当前获取的缓冲区之间的最大允许距离。或者，可以由定时器提供放弃缓冲器的所有权的I / O设备的条件。定时器可以指定I / O设备可以维持特定缓冲器的所有权的最大时间。在其他实现中，提供了一种机制来强制I / O设备放弃其控制的一些或全部缓冲区。

2. 发明申请

US20110055346A1 DIRECT MEMORY ACCESS BUFFER MANAGEMENT 有权
标题翻译：直接存储器访问缓冲器管理
公开(公告)号：US20110055346A1
公开(公告)日：2011-03-03
申请号：US12550005
申请日：2009-08-28
申请人： Ajoy Siddabathuni , Arvind Srinivasan , Shimon Muller
发明人： Ajoy Siddabathuni , Arvind Srinivasan , Shimon Muller
IPC分类号： G06F15/167 , G06F3/00
CPC分类号： G06F13/28
摘要： Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.
摘要翻译：公开了用于在通过网络进行数据传输的输入/输出设备（I / O设备）执行的直接存储器访问（DMA）操作期间回收缓冲器的系统和方法。在数据传输期间，I / O设备可以取消由设备驱动器提供的缓冲器，从而放弃缓冲器的所有权。放弃缓冲器所有权的I / O设备的条件可以由可能与缓冲器相关联的距离向量来提供。距离向量可以指定缓冲区和I / O设备当前获取的缓冲区之间的最大允许距离。或者，可以由定时器提供放弃缓冲器的所有权的I / O设备的条件。定时器可以指定I / O设备可以维持特定缓冲器的所有权的最大时间。在其他实现中，提供了一种机制来强制I / O设备放弃其控制的一些或全部缓冲区。

3. 发明授权

US08555867B2 Energy efficient plasma generation 失效
标题翻译：节能等离子体生成
公开(公告)号：US08555867B2
公开(公告)日：2013-10-15
申请号：US12819146
申请日：2010-06-18
申请人： Arvind Srinivasan , Karthikeyan Ramanathan , Luc Choquette , Aaron Murakami
发明人： Arvind Srinivasan , Karthikeyan Ramanathan , Luc Choquette , Aaron Murakami
IPC分类号： F02P3/02
CPC分类号： F02P17/12 , F02P3/005 , F02P3/0442 , F02P9/007
摘要： A plasma ignition system is described herein that can produce plasma ionization around a spark plug gap using a single power circuit for the spark and plasma ionization. The system results in fewer components and higher reliability, allowing the system to be more easily integrated with existing ignition circuitry or in new ignition system designs. The plasma ignition system adds a one-way current path between the primary and secondary windings of the high voltage transformer. This allows energy stored within the capacitor after the creation of the spark to flow out of the capacitor, across the one-way current path, and through the spark plug gap. Thus, the plasma ignition system provides a dramatically better ignition spark with relatively little increase in components. The system does so without requiring a secondary power supply circuit to generate the current for producing plasma ionization.
摘要翻译：本文描述了等离子体点火系统，其可以使用用于火花和等离子体电离的单个功率电路在火花塞间隙周围产生等离子体电离。该系统导致更少的部件和更高的可靠性，使系统更容易与现有的点火电路或新的点火系统设计集成。等离子体点火系统在高压变压器的初级和次级绕组之间增加一个单向电流通路。这允许在产生火花之后存储在电容器内的能量流过电容器，跨越单向电流路径并通过火花塞间隙。因此，等离子体点火系统提供了显着更好的点火火花，组件的增加相对较小。该系统不需要二次电源电路来产生用于产生等离子体电离的电流。

4. 发明申请

US20130080627A1 SYSTEM AND METHOD FOR SURGE PROTECTION AND RATE ACCELERATION IN A TRAFFIC DIRECTOR ENVIRONMENT 有权
标题翻译：交通主管环境中的防护和速率加速系统及方法
公开(公告)号：US20130080627A1
公开(公告)日：2013-03-28
申请号：US13601428
申请日：2012-08-31
申请人： Basant Kukreja , Zhong Xu , Adam Leftik , Arvind Srinivasan
发明人： Basant Kukreja , Zhong Xu , Adam Leftik , Arvind Srinivasan
IPC分类号： G06F11/30
CPC分类号： G06F9/505 , G06F9/451 , G06F9/45512 , G06F11/2041 , G06F11/3433 , G06F17/276 , G06F2201/86 , H04L41/08 , H04L63/0853 , H04L67/1002 , H04L67/1008 , H04L67/1034 , H04L2029/06054
摘要： Described herein are systems and methods for use with a load balancer or traffic director, and administration thereof. In accordance with an embodiment the system comprises a traffic director having one or more traffic director instances, which is configured to receive and communicate requests, from clients, to origin servers having one or more pools of servers. A traffic monitor, at the traffic director, monitors traffic, including the number of connections, between the traffic director instances and one or more of the resource servers within the origin servers. The traffic director can set a traffic rate which controls the traffic, including the number of connections, to provide surge protection, or rate acceleration/deceleration.
摘要翻译：这里描述了与负载平衡器或交通导向器一起使用的系统和方法及其管理。根据一个实施例，系统包括具有一个或多个业务导向器实例的业务指挥器，其被配置为从客户端接收和传送请求到具有一个或多个服务器池的源服务器。流量监控器在流量监控器上监视流量指导器实例与源服务器内的一个或多个资源服务器之间的流量，包括连接数。交通总监可以设置一个流量控制流量，包括连接数量，提供浪涌保护，加速/减速率。

5. 发明授权

US08145967B2 System and method for verifying the receive path of an input/output component 有权
标题翻译：用于验证输入/输出组件的接收路径的系统和方法
公开(公告)号：US08145967B2
公开(公告)日：2012-03-27
申请号：US11974414
申请日：2007-10-12
申请人： Arvind Srinivasan , Rahoul Puri
发明人： Arvind Srinivasan , Rahoul Puri
IPC分类号： G06F11/00
CPC分类号： G06F11/277
摘要： A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.
摘要翻译：一种用于验证诸如网络接口电路的输入/输出设备的接收路径的系统和方法。该设备利用各种不同的输入源（例如网络）和输出源（例如，主机，主机总线）的操作被建模在采用多个队列来模拟分组的接收，计算目的地址和分组数据的存储的验证层中通过设备。采用回叫信号来完成与设备的分组数据的存储相关的事件以及验证层内数据处理的建模。根据设备策略建模的动态DMA策略，对验证层内的令牌进行处理以模拟设备对相应数据包的处理。该策略是动态的，可以在验证过程中进行更新或替换，而不会中断验证过程。

6. 发明申请

US20110282715A1 BUSINESS ACTIVITY MONITORING ANOMALY DETECTION 失效
标题翻译：业务活动监测异常检测
公开(公告)号：US20110282715A1
公开(公告)日：2011-11-17
申请号：US12778916
申请日：2010-05-12
申请人： Kiet Nguyen , Annapureddy S. Reddy , Arvind Srinivasan , Shubha S. Tangirala
发明人： Kiet Nguyen , Annapureddy S. Reddy , Arvind Srinivasan , Shubha S. Tangirala
IPC分类号： G06Q10/00 , G06F9/46
CPC分类号： G06Q10/06 , G06Q10/06393
摘要： An anomaly detector compares a first event from a business activity monitoring system to a second number from an independent trusted source, wherein the first event includes a first number. The anomaly detector determines that the first number from the business activity monitoring system is inconsistent with the second number. The anomaly detector generates a calibration relationship between first number and second number based on time, responsive to a determination that the first number is inconsistent with the second number. The anomaly detector stores the calibration relationship. The anomaly detector receives a third number from the business activity monitoring system at an interval after comparing the first number. The anomaly detector displays the third number to a dashboard. The anomaly detector displays a qualifier to the third number.
摘要翻译：异常检测器将来自业务活动监视系统的第一事件与来自独立可信源的第二事件进行比较，其中第一事件包括第一号。异常检测器确定来自业务活动监视系统的第一个数字与第二个数字不一致。异常检测器响应于第一个数字与第二个数字不一致的确定，基于时间产生第一个数量和第二个数量之间的校准关系。异常检测器存储校准关系。异常检测器在比较第一个数字之后的间隔从业务活动监视系统接收第三个数字。异常检测器将第三个数字显示给仪表板。异常检测器显示第三个数字的限定符。

7. 发明授权

US07958476B1 Method for multi-cycle path and false path clock gating 有权
标题翻译：多周期路径和假路径时钟门控的方法
公开(公告)号：US07958476B1
公开(公告)日：2011-06-07
申请号：US12170354
申请日：2008-07-09
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A power optimization method of deriving gated circuitry in an integrated circuit (IC) is provided. A design description of the IC is received and analyzed. A state machine is identified based on the analysis. One or more candidate blocks are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states of the state machine. A gating circuit is inserted for gating the selected candidate block(s). In another embodiment of power optimization, one or more state machines are identified and a synthesized netlist is generated. One or more candidate blocks in the synthesized netlist are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states in the state machine, and a gating circuit is inserted for gating the selected candidate block(s).
摘要翻译：提供了一种在集成电路（IC）中导出门控电路的功率优化方法。接收并分析IC的设计描述。基于分析识别状态机。一个或多个候选块被确定为能够被禁用。基于状态机的一个或多个状态来选择候选块中的至少一个。插入门控电路以选通候选块。在功率优化的另一个实施例中，识别一个或多个状态机，并且生成合成的网表。合成网表中的一个或多个候选块被确定为能够被禁用。基于状态机中的一个或多个状态来选择候选块中的至少一个，并且插入门控电路以门控所选择的候选块。

8. 发明授权

US07860975B2 System and method for secure sticky routing of requests within a server farm 有权
标题翻译：系统和方法，用于在服务器场内的请求的安全粘性路由
公开(公告)号：US07860975B2
公开(公告)日：2010-12-28
申请号：US10209036
申请日：2002-07-31
申请人： Christopher H. Elving , Arvind Srinivasan
发明人： Christopher H. Elving , Arvind Srinivasan
IPC分类号： G06F15/16
CPC分类号： H04L67/1008 , H04L67/1002
摘要： Upstream devices, such as load balancers or routers, within a server farm, may be configured to route requests to the servers handling sessions for those requests using a secure (e.g. encrypted) unique ID or network address received with requests identifying how requests may be routed through the server farm. Upstream devices or a server receiving a request that is not associated with a session may generate a unique ID or select a network address identifying how the request is routed through the server farm. The server handling the request forms a session ID and returns that session ID and the unique ID to the client that originated the request. Encryption may be performed on network addresses or session IDs. Upon receiving a request corresponding to an established session, an upstream device may then decrypt routing information from the encrypted unique ID or network address and send the request downstream accordingly.
摘要翻译：服务器场内的上游设备（例如负载平衡器或路由器）可以被配置为使用安全（例如加密的）唯一ID或网络地址将请求路由到服务器处理那些请求的会话，该唯一ID或网络地址通过识别请求如何被路由的请求而被接收通过服务器场。上游设备或接收与会话不相关联的请求的服务器可以生成唯一的ID或选择标识请求如何通过服务器场路由的网络地址。处理请求的服务器形成会话ID，并将该会话ID和唯一ID返回给发起请求的客户端。可以对网络地址或会话ID执行加密。一旦接收到与建立的会话相对应的请求，上游设备就可以从加密的唯一ID或网络地址中解密路由信息，并相应地发送请求。

9. 发明授权

US07222426B2 Method of forming a constant velocity joint 失效
标题翻译：形成恒速接头的方法
公开(公告)号：US07222426B2
公开(公告)日：2007-05-29
申请号：US10755805
申请日：2004-01-12
申请人： Michael W. Hopson , Glenn C. Ringle , Richard L. Seidel , Arvind Srinivasan
发明人： Michael W. Hopson , Glenn C. Ringle , Richard L. Seidel , Arvind Srinivasan
IPC分类号： B23P17/00
CPC分类号： B23P15/00 , B21K1/762 , B21K1/765 , B23P2700/11 , F16D2250/00 , Y10T29/49636 , Y10T29/49684 , Y10T29/49689
摘要： The present invention is directed to a constant velocity joint (“CV joint”) and, more particularly, to a Rzeppa CV joint and method of forming the same. The method generally includes the steps of forming a bell shaped outer bearing race and separating the bell shaped outer bearing race into a disc shaped outer bearing race and a stub shaft. The method may further include the step of machining the bell shaped outer bearing race to create the stub shaft integrally connected to the disc shaped outer bearing race, before separating the bell shaped outer bearing race into the disc shaped outer bearing race and the stub shaft.
摘要翻译：本发明涉及等速万向节（“CV接头”），更具体地说，涉及一种Rzeppa CV接头及其形成方法。该方法通常包括形成钟形外部轴承座圈并将钟形外部轴承座圈分离成盘形外部轴承座和短轴的步骤。该方法可以进一步包括在将钟形外轴承座圈分离成盘形外轴承座和短轴之前，加工钟形外轴承座以产生一体地连接到盘形外轴承座的短轴。

10. 发明授权

US06993617B2 System-on-a-chip having an on-chip processor and an on-chip dynamic random access memory (DRAM) 有权
公开(公告)号：US06993617B2
公开(公告)日：2006-01-31
申请号：US10393865
申请日：2003-03-21
申请人： Lawrence Butcher , Duane Northcutt , Marc Schneider , Jerry Wall , James Hanko , Alan Ruberg , Satyanarayana Simha , Michael E. Duboce , Arvind Srinivasan
发明人： Lawrence Butcher , Duane Northcutt , Marc Schneider , Jerry Wall , James Hanko , Alan Ruberg , Satyanarayana Simha , Michael E. Duboce , Arvind Srinivasan
IPC分类号： G06F13/00 , G06F13/38 , G06F13/40
CPC分类号： G06F15/786 , G06F15/7842
摘要： A system-on-a-chip device is provided, the system-on-a-chip device comprising an on-chip processor and an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip device also comprises at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).

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