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1. 发明申请

US20070290237A1 INSULATED GATE BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：绝缘栅双极晶体管及其制造方法
公开(公告)号：US20070290237A1
公开(公告)日：2007-12-20
申请号：US11763558
申请日：2007-06-15
申请人： Akio NAKAGAWA
发明人： Akio NAKAGAWA
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/36
摘要： An insulated gate bipolar transistor has a p-type emitter layer; an n-type buffer layer provided on the p-type emitter layer; an n-type base layer provided on the n-type buffer layer and having a higher resistivity than the n-type buffer layer; a p-type base layer provided in part of an upper surface of the n-type base layer; an n-type source layer provided in part of an upper surface of the p-type base layer; a trench extending through the n-type source layer and the p-type base layer to the n-type base layer; a gate electrode provided in the trench; and a gate insulating film provided between the gate electrode and an inner surface of the trench. The p-type emitter layer has a thickness of 5 to 50 μm and a dopant concentration of 2×1016 to 1×1018 cm−3.
摘要翻译：绝缘栅双极晶体管具有p型发射极层; 设置在p型发射极层上的n型缓冲层; 设置在n型缓冲层上并具有比n型缓冲层更高的电阻率的n型基极层; 设置在n型基底层的上表面的一部分的p型基底层; 设置在p型基底层的上表面的一部分的n型源极层; 通过n型源极层和p型基极层延伸到n型基极层的沟槽; 设置在沟槽中的栅电极; 以及栅极绝缘膜，设置在所述栅电极和所述沟槽的内表面之间。 p型发射极层的厚度为5〜50μm，掺杂剂浓度为2×10 16〜1×10 8 cm -3以下。

2. 发明申请

US20080185640A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080185640A1
公开(公告)日：2008-08-07
申请号：US12050822
申请日：2008-03-18
申请人： Akio NAKAGAWA
发明人： Akio NAKAGAWA
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66727
摘要： A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and a fifth semiconductor layer of the first conduction type are stacked on the surfaces of the second and third semiconductor layers. The semiconductor device further comprises a control electrode formed in a trench with an insulator interposed therebetween. The trench passes through the fourth and fifth semiconductor layers and reaches the second semiconductor layer. A sixth semiconductor layer of the first conduction type is diffused from the bottom of the trench. A second main electrode is connected to the fourth and fifth semiconductor layers.
摘要翻译：第一主电极设置在其一个表面上。在其另一个表面上，第一导电类型的第二半导体层和第二导电类型的第三半导体层沿表面交替布置。第二导电类型的第四半导体层和第一导电类型的第五半导体层堆叠在第二和第三半导体层的表面上。半导体器件还包括形成在沟槽中的控制电极，绝缘体插入其间。沟槽穿过第四和第五半导体层并到达第二半导体层。第一导电类型的第六半导体层从沟槽的底部扩散。第二主电极连接到第四和第五半导体层。

3. 发明申请

US20120256607A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120256607A1
公开(公告)日：2012-10-11
申请号：US13527678
申请日：2012-06-20
申请人： Kazutoshi NAKAMURA , Toru TAKAYAMA , Yuki KAMATA , Akio NAKAGAWA , Yoshinobu SANO , Toshiyuki NAKA
发明人： Kazutoshi NAKAMURA , Toru TAKAYAMA , Yuki KAMATA , Akio NAKAGAWA , Yoshinobu SANO , Toshiyuki NAKA
IPC分类号： G05F1/00
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

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