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1. 发明申请

US20180309456A1 PHASE COMBINER CIRCUIT 审中-公开
公开(公告)号：US20180309456A1
公开(公告)日：2018-10-25
申请号：US15495521
申请日：2017-04-24
申请人： Infineon Technologies AG
发明人： Werner Grollitsch
IPC分类号： H03L7/085 , H03K3/037
CPC分类号： H03L7/085 , H03K5/00006
摘要： Methods and devices are discussed where a plurality of input signals having different phases are provided. From the input signals, a plurality of signal pairs are selected, and intermediate signals are generated based on the signal pairs. The intermediate signals are then combined.

2. 发明申请

US20180278210A1 INTEGRATED CIRCUIT COMPRISING FRACTIONAL CLOCK MULTIPLICATION CIRCUITRY 审中-公开
公开(公告)号：US20180278210A1
公开(公告)日：2018-09-27
申请号：US15921480
申请日：2018-03-14
申请人： Rambus Inc.
发明人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
IPC分类号： H03B19/00 , H03K3/03 , G06F1/10 , G06F1/08 , H03K5/00 , H03L7/099
CPC分类号： H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099 , H05K999/99
摘要： Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

3. 发明申请

US20180269886A1 Method and Device for Doubling the Frequency of a Reference Signal of a Phase Locked Loop 审中-公开
公开(公告)号：US20180269886A1
公开(公告)日：2018-09-20
申请号：US15800302
申请日：2017-11-01
申请人： STMicroelectronics SA
发明人： Marc Houdebine , Sebastien Dedieu
IPC分类号： H03L7/197 , H03L7/089 , H04L7/033
CPC分类号： H03L7/1974 , H03K5/00006 , H03L7/0891 , H03L7/1976 , H03L2207/10 , H04L7/0331
摘要： In some embodiments, a phase locked loop includes a voltage-controlled oscillator whose output is fed back to a first input of a phase comparator via a fractional divider controlled by a delta-sigma modulator. The method of doubling the frequency of the initial reference signal of the phase locked loop involves generating, from the initial reference signal and the output signal furnished by the voltage-controlled oscillator, a secondary reference signal having edges of a first type synchronized with each of the rising and falling edges of the initial reference signal and edges of a second type between the edges of the first type, and a furnishing of the secondary reference signal at a second input of the phase comparator operating on the edges of the first type.

4. 发明申请

US20180205383A1 Digital Clock Generation and Variation Control Circuitry 审中-公开
公开(公告)号：US20180205383A1
公开(公告)日：2018-07-19
申请号：US15410574
申请日：2017-01-19
申请人： QUALCOMM Incorporated
发明人： Farshid Nowshadi , John Bruce
IPC分类号： H03L7/08 , H03K5/133
CPC分类号： H03L7/08 , G06F1/08 , G06F1/10 , H03K5/00006 , H03K5/133 , H03K2005/00019
摘要： In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.

5. 发明授权

US09973177B1 Clock generator with injection-locking oscillators 有权
公开(公告)号：US09973177B1
公开(公告)日：2018-05-15
申请号：US15360149
申请日：2016-11-23
申请人： Rambus Inc.
发明人： Yue Lu , Jared L. Zerbe
IPC分类号： H03B19/00 , H03K5/00 , H03L7/099 , H03L7/24
CPC分类号： H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
摘要： In a clock generating circuit having a plurality of injection-locking oscillators, a first one of the injection-locking oscillators is enabled to output a free-running reference clock signal and a control value is generated based at least in part on a frequency relationship between the free-running reference clock signal and an input timing signal. In accordance with the control value, a selected one of the injection-locking oscillators is enabled to generate an output clock signal that is frequency-locked with respect to the input timing signal.

6. 发明申请

US20170207774A1 D LATCH CIRCUIT 审中-公开
公开(公告)号：US20170207774A1
公开(公告)日：2017-07-20
申请号：US15408412
申请日：2017-01-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Diptendu Ghosh , Petteri Matti Litmanen , Siraj Akhtar
IPC分类号： H03K5/00 , H03K3/356
CPC分类号： H03K5/00006 , H03K3/356139
摘要： A latch circuit includes first and second inverters, each with latching (inner) and clocking (outer) PMOS/NMOS transistor pairs in a series/stack configuration. A first inverter includes a D_latching PMOS/NMOS transistor pair, drain-connected at a D node. A first /clock PMOS transistor is coupled between a high rail and a source terminal of the D_latching PMOS transistor, and a first clock NMOS transistor is coupled between a low rail and the source terminal of the D_latching NMOS transistor. A second inverter includes a Dbar_latching PMOS/NMOS transistor pair, drain-connected at a Dbar node. A second /clock PMOS transistor is coupled between the high rail and the source terminal of the Dbar_latching PMOS transistor, and a second clock NMOS transistor is coupled between the low rail and the Dbar_latching NMOS transistor. A cross-coupling switch circuit connected between the D node and the Dbar node. The first and second /clock PMOS transistors can be combined as a single /clock PMOS transistor connected between the high rail and the source terminals of respectively the D_latching and Dbar_latching PMOS transistors, and the first and second clock NMOS transistors can be combined as a single clock NMOS transistor connected between the low rail and the source terminals of respectively the D_latching and Dbar_latching NMOS transistors. As an example application, the latch circuit can be used in a quadrature (IQ) frequency divider.

7. 发明申请

US20170149420A1 FREQUENCY MULTIPLIER 有权
公开(公告)号：US20170149420A1
公开(公告)日：2017-05-25
申请号：US15231053
申请日：2016-08-08
申请人： Mitsubishi Electric Corporation
发明人： Hitoshi KURUSU , Takumi SUGITANI
IPC分类号： H03K5/00 , H03H11/30
CPC分类号： H03K5/00006 , H03H11/30
摘要： A frequency includes an input terminal, an output terminal, a transistor having a gate terminal which receives input of a signal including a first frequency from the input terminal, a source terminal and a drain terminal connected to the output terminal by a main line, an output matching circuit provided in the main line, the output matching circuit shutting off the first frequency while allowing an output frequency multiplied from the first frequency to pass therethrough, a branch line including a power supply terminal for connection to a power supply, the branch line branching off from a branch point in the main line, and a first diode provided in the branch line, the first diode having an anode connected to the power supply terminal and a cathode connected on the branch point side.

8. 发明授权

US09628057B2 Spread-spectrum clock generation circuit, integrated circuit and apparatus therefor 有权
公开(公告)号：US09628057B2
公开(公告)日：2017-04-18
申请号：US14909212
申请日：2013-08-01
申请人： Denis Sergeevich Shuvalov
发明人： Denis Sergeevich Shuvalov
IPC分类号： G06F1/04 , H03K5/00 , H03K3/0231 , H03K25/02
CPC分类号： H03K5/00006 , H03J2200/10 , H03K3/0231 , H03K25/02
摘要： A spread-spectrum clock generation circuit comprises at least one comparison element; at least one charge storage device arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a first oscillation frequency of the spread-spectrum clock generation circuit; and a switched charge storage arrangement additionally arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a second oscillation frequency of the spread-spectrum clock generation circuit.

9. 发明授权

US09614504B2 Electronic device and clock control method thereof 有权
公开(公告)号：US09614504B2
公开(公告)日：2017-04-04
申请号：US14742227
申请日：2015-06-17
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Gun-young Bae , Dong-bin Park
IPC分类号： G06F1/04 , H03K5/00 , H03L7/08 , H04B10/116 , H04L7/00 , G01J1/02 , H03K7/08
CPC分类号： H03K5/00006 , G01J1/02 , H03K7/08 , H03L7/08 , H03L2207/50 , H04B10/1149 , H04B10/116 , H04L7/0012
摘要： A user terminal device and a display method thereof are provided. A method for controlling a clock according to an exemplary embodiment includes generating a clock, generating a comparison clock corresponding to a frequency of an external alternating current (AC) power source, counting a number of clock cycles according to the comparison clock, and controlling a generation period of the clock according to the counted number of clock cycles.

10. 发明授权

US09531391B1 Frequency-agile clock multiplier 有权
标题翻译：频率敏捷时钟倍频器
公开(公告)号：US09531391B1
公开(公告)日：2016-12-27
申请号：US14715537
申请日：2015-05-18
申请人： Rambus Inc.
发明人： Yue Lu , Jared L. Zerbe
IPC分类号： H03L7/06 , H03L7/08 , H04L7/033 , H03L7/085 , H03L7/099
CPC分类号： H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
摘要： Upon detecting transition of an input timing signal from a non-oscillating state to an oscillating state, a clock generating circuit is switched from a paused mode to an open-loop operating mode to transition an output timing signal of the clock generating circuit from a non-oscillating state to an oscillating state in which the output timing signal oscillates at a free-running frequency. A ratio of a reference frequency of the oscillating-state input timing signal and the free-running frequency of the output timing signal is determined and used to adjust a frequency-lock range of the clock generating circuit. The clock generating circuit is then switched from the open-loop operating state to the closed-loop operating state to frequency-lock the output timing signal with respect to the reference frequency of the input timing signal.
摘要翻译：当检测到输入定时信号从非振荡状态向振荡状态的转变时，时钟发生电路从暂停模式切换到开环工作模式，以将时钟产生电路的输出定时信号从非振荡状态到输出定时信号以自由运行频率振荡的振荡状态。确定振荡状态输入定时信号的参考频率与输出定时信号的自由运行频率的比率，并用于调整时钟发生电路的频率锁定范围。然后，时钟产生电路从开环工作状态切换到闭环工作状态，以相对于输入定时信号的参考频率对输出定时信号进行频率锁定。

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