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1. 发明申请

US20070080405A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070080405A1
公开(公告)日：2007-04-12
申请号：US11542269
申请日：2006-10-04
申请人： Naoki Kotani , Gen Okazaki , Shinji Takeoka , Junji Hirase , Akio Sebe , Kazuhiko Aida
发明人： Naoki Kotani , Gen Okazaki , Shinji Takeoka , Junji Hirase , Akio Sebe , Kazuhiko Aida
IPC分类号： H01L29/94
CPC分类号： H01L21/28097 , H01L21/28123 , H01L29/4975 , H01L29/66545
摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.
摘要翻译：半导体器件包括：形成在半导体衬底中的隔离区; 由半导体衬底中的隔离区围绕的有源区; 形成在有源区上的栅极绝缘膜; 以及形成在有源区域和邻近有源区域的隔离区域之间的边界上的栅电极。栅电极包括位于有源区上方的第一部分，栅极绝缘膜插入其间，并且在厚度方向上完全由硅化物制成，而第二部分位于隔离区上方，并由硅区域以及覆盖硅区域的硅化物区域。

2. 发明申请

US20070045695A1 Method for fabricating semiconductor device and semiconductor device 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20070045695A1
公开(公告)日：2007-03-01
申请号：US11491936
申请日：2006-07-25
申请人： Shinji Takeoka , Akio Sebe , Junji Hirase , Naoki Kotani , Gen Okazaki , Kazuhiko Aida
发明人： Shinji Takeoka , Akio Sebe , Junji Hirase , Naoki Kotani , Gen Okazaki , Kazuhiko Aida
IPC分类号： H01L29/94
CPC分类号： H01L21/82345 , H01L21/28097 , H01L21/3212 , H01L21/823443 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： A Ni film is deposited over the entire surface of a substrate including a silicon gate. Then, the silicon gate is partially removed by, for example, CMP, thereby leaving a Ni layer having a flat upper surface and a uniform thickness directly on the silicon gate. Subsequently, silicidation is performed, thereby forming a gate electrode having a uniform silicide phase.
摘要翻译：在包括硅栅极的衬底的整个表面上沉积Ni膜。然后，通过例如CMP部分去除硅栅极，由此在硅栅极上直接留下具有平坦的上表面和均匀厚度的Ni层。随后，进行硅化，从而形成具有均匀硅化物相的栅电极。

3. 发明授权

US08587076B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08587076B2
公开(公告)日：2013-11-19
申请号：US13547913
申请日：2012-07-12
申请人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
发明人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
IPC分类号： H01L29/76 , H01L29/94 , H01L27/108 , H01L31/119 , H01L31/062
CPC分类号： H01L29/4983 , H01L29/42368 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
摘要翻译：半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

4. 发明授权

US08253180B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08253180B2
公开(公告)日：2012-08-28
申请号：US13037831
申请日：2011-03-01
申请人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
发明人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L29/42368 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
摘要翻译：半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

5. 发明申请

US20110147857A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110147857A1
公开(公告)日：2011-06-23
申请号：US13037831
申请日：2011-03-01
申请人： Junji HIRASE , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
发明人： Junji HIRASE , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
IPC分类号： H01L29/772
CPC分类号： H01L29/4983 , H01L29/42368 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
摘要翻译：半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

6. 发明授权

US07732839B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07732839B2
公开(公告)日：2010-06-08
申请号：US11525011
申请日：2006-09-22
申请人： Akio Sebe , Naoki Kotani , Shinji Takeoka , Gen Okazaki , Junji Hirase , Kazuhiko Aida
发明人： Akio Sebe , Naoki Kotani , Shinji Takeoka , Gen Okazaki , Junji Hirase , Kazuhiko Aida
IPC分类号： H01L27/10
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source/drain regions and a stress film formed so as to cover the gate electrode portion and the source/drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source/drain regions.
摘要翻译： MIS晶体管包括栅电极部分，形成在栅电极部分的侧表面上的绝缘侧壁，源极/漏极区域和形成为覆盖栅电极部分和源极/漏极区域的应力膜。栅电极部分的上表面的高度小于每个绝缘侧壁的上边缘的高度。位于栅电极部分的应力膜的第一部分的厚度大于位于源/漏区上的应力膜的第二部分的厚度。

7. 发明授权

US07923764B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07923764B2
公开(公告)日：2011-04-12
申请号：US12505799
申请日：2009-07-20
申请人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
发明人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L29/42368 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
摘要翻译：半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

8. 发明授权

US07646065B2 Semiconductor device including fully-silicided (FUSI) gate electrodes 有权
标题翻译：半导体器件包括全硅化（FUSI）栅电极
公开(公告)号：US07646065B2
公开(公告)日：2010-01-12
申请号：US11542269
申请日：2006-10-04
申请人： Naoki Kotani , Gen Okazaki , Shinji Takeoka , Junji Hirase , Akio Sebe , Kazuhiko Aida
发明人： Naoki Kotani , Gen Okazaki , Shinji Takeoka , Junji Hirase , Akio Sebe , Kazuhiko Aida
IPC分类号： H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28097 , H01L21/28123 , H01L29/4975 , H01L29/66545
摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.
摘要翻译：半导体器件包括：形成在半导体衬底中的隔离区; 由半导体衬底中的隔离区围绕的有源区; 形成在有源区上的栅极绝缘膜; 以及形成在有源区域和邻近有源区域的隔离区域之间的边界上的栅电极。栅电极包括位于有源区上方的第一部分，栅极绝缘膜插入其间，并且在厚度方向上完全由硅化物制成，而第二部分位于隔离区上方，并由硅区域以及覆盖硅区域的硅化物区域。

9. 发明授权

US07579227B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07579227B2
公开(公告)日：2009-08-25
申请号：US11491260
申请日：2006-07-24
申请人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
发明人： Junji Hirase , Akio Sebe , Naoki Kotani , Gen Okazaki , Kazuhiko Aida , Shinji Takeoka
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/76 , H01L29/94 , H01L27/108
CPC分类号： H01L29/4983 , H01L29/42368 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.
摘要翻译：半导体器件包括：形成在衬底的有源区上的高介电常数栅极绝缘膜; 形成在高介电常数栅极绝缘膜上的栅电极; 以及形成在栅电极的每个侧表面上的绝缘侧壁。高介电常数栅极绝缘膜连续地形成为从栅极下方延伸到绝缘侧壁下方。位于绝缘侧壁下方的高介电常数栅极绝缘膜的至少一部分的厚度比位于栅电极下方的高介电常数栅极绝缘膜的厚度的厚度小。

10. 发明申请

US20070069304A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070069304A1
公开(公告)日：2007-03-29
申请号：US11450349
申请日：2006-06-12
申请人： Kazuhiko Aida , Junji Hirase , Akio Sebe , Naoki Kotani , Shinji Takeoka , Gen Okazaki
发明人： Kazuhiko Aida , Junji Hirase , Akio Sebe , Naoki Kotani , Shinji Takeoka , Gen Okazaki
IPC分类号： H01L29/94
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/823871
摘要： A semiconductor device includes: a first element region and a second element region formed on a substrate to be adjacent to each other with an isolation region interposed therebetween; a first gate insulating film formed on the first element region; a second gate insulating film formed on the second element region; and a gate electrode continuously formed on the first gate insulating film, the isolation region and the second gate insulating film. The gate electrode includes a first silicided region formed to come into contact with the first gate insulating film, a second silicided region which is formed to come into contact with the second gate insulating film and is of a different composition from the first silicided region, and a conductive anti-diffusion region composed of a non-silicided region formed in a part of the gate electrode located on the isolation region and between the first element region and the second element region.
摘要翻译：半导体器件包括：第一元件区域和第二元件区域，其形成在彼此相邻并且隔着隔离区域彼此相邻的基板上; 形成在所述第一元件区域上的第一栅极绝缘膜; 形成在所述第二元件区域上的第二栅极绝缘膜; 以及连续地形成在第一栅极绝缘膜，隔离区域和第二栅极绝缘膜上的栅电极。栅电极包括形成为与第一栅极绝缘膜接触的第一硅化物区域，形成为与第二栅极绝缘膜接触并且与第一硅化物区域具有不同组成的第二硅化物区域，以及由形成在位于隔离区上的栅电极的一部分之间以及第一元件区与第二元件区之间的非硅化区构成的导电抗扩散区。

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