会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • Class D Amplifier Control Circuit and Method
    • D类放大器控制电路及方法
    • US20110006844A1
    • 2011-01-13
    • US12858310
    • 2010-08-17
    • Eric SoenenAlan RothJustin ShiMartin Kinyua
    • Eric SoenenAlan RothJustin ShiMartin Kinyua
    • H03F3/217
    • H03F3/2173
    • Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
    • D类放大器的电路和方法。 在一个示例性实施例中,公开了一种音频放大器。 提供用于驱动高侧和低侧驱动晶体管的闭环配置,每个电路与先进的亚微米半导体工艺兼容。 模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。 来自输出的反馈信号也被输入到模数转换器。 位流由模数转换器输出。 抽取器接收该位流,并以较低的频率将样本下变频为数字值。 使用具有适应系数的数字滤波器来对该信号进行滤波,并且数字脉宽调制器然后开发模拟差分PWM信号。 预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。
    • 6. 发明申请
    • CLASS D AMPLIFIER CONTROL CIRCUIT AND METHOD
    • 等级放大器控制电路和方法
    • US20100045376A1
    • 2010-02-25
    • US12197967
    • 2008-08-25
    • Eric SoenenAlan RothJustin Shi
    • Eric SoenenAlan RothJustin Shi
    • H03F3/217
    • H03F3/2173
    • Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.
    • D类放大器的电路和方法。 在一个示例性实施例中,公开了一种音频放大器。 提供用于驱动高侧和低侧驱动晶体管的闭环配置,每个电路与先进的亚微米半导体工艺兼容。 模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。 来自输出的反馈信号也被输入到模数转换器。 位流由模数转换器输出。 抽取器接收该位流,并以较低的频率将样本下变频为数字值。 使用具有适应系数的数字滤波器来对该信号进行滤波,并且数字脉宽调制器然后开发模拟差分PWM信号。 预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。
    • 7. 发明授权
    • Idle tone suppression circuit
    • 空闲音抑制电路
    • US08547267B2
    • 2013-10-01
    • US13481990
    • 2012-05-29
    • Alan RothEric SoenenChia Liang Tai
    • Alan RothEric SoenenChia Liang Tai
    • H03M3/00
    • G05B11/01G01K7/16G01K15/005G05B15/02H03M3/344H03M3/458
    • A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.
    • 迟滞数字滤波器包括具有用于接收一系列多比特Σ-ΔADC码的输入的第一多位触发器,用于接收时钟信号和输出的时钟输入; 具有耦合到第一多位触发器的输出的输入的第二多位触发器,用于提供数字滤波器的输出码的输出和用于接收锁存控制信号的输入,第二多位触发器 位触发器在锁存控制信号的控制下将其输入锁存到其输出端; 和控制电路。 控制电路被配置为根据数字滤波器的输出代码的运行比较和多比特Σ-位触发器的各个值的选择性地提供锁存控制信号以触发第二多位触发器的锁存, 来自多位Σ-ΔADC代码的Delta ADC代码。