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1. 发明授权

US07757137B2 Method and apparatus for on-the-fly minimum power state transition 失效
标题翻译：用于实时最小功率状态转换的方法和装置
公开(公告)号：US07757137B2
公开(公告)日：2010-07-13
申请号：US11691856
申请日：2007-03-27
申请人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
发明人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575
摘要： The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation. The switching occurs in only one clock cycle.
摘要翻译：本发明包括用于LSSD或GSD IC操作的新型扫描链结构。扫描链结构包括在扫描模式操作中，在初始化模式和低泄漏状态下，被配置为在正常模式操作中操作第一触发器（L1）的第一触发器（L1）和第二触发器（L2）功率模式操作，其中锁存器的长扫描链内的每个触发器包括布置用于正常模式操作的数据输入，数据输出，时钟输入，扫描输入和扫描输出输出。缓冲电路电连接在第二触发器（L2）的扫出输出端和第一触发器（L1）的扫描输入端之间用于扫描链中的下一个锁存器，缓冲电路包括一个控制元件，其控制第一触发器（L1）的扫描模式或低功率泄漏模式的操作。在从低功率泄漏模式退出时，第一触发器（L1）被设置为数据输出值，该值是在正常模式操作期间初始化时被设置为相同的值。开关仅在一个时钟周期内发生。

2. 发明授权

US07949971B2 Method and apparatus for on-the-fly minimum power state transition 有权
标题翻译：用于实时最小功率状态转换的方法和装置
公开(公告)号：US07949971B2
公开(公告)日：2011-05-24
申请号：US11966493
申请日：2007-12-28
申请人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
发明人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
IPC分类号： G06F17/50 , H01L25/00 , H03K19/00
CPC分类号： G06F17/5045 , G01R31/318536 , G01R31/318575 , G06F2217/14 , G06F2217/78
摘要： The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one clock cycle. The design structure can include a netlist, which describes the VLSI circuit, reside on storage medium as a data format used for the exchange of layout data of integrated circuits, and preferably includes at least one of test data files, characterization data, verification data, or design specifications.
摘要翻译：本发明包括体现在计算机可读介质中的设计结构，用于执行将扫描链插入到VLSI电路设计中的方法。扫描链结构或结构包含在VLSI电路设计的设计结构中。扫描链结构包括在扫描模式操作中，在初始化模式和低泄漏状态下，被配置为在正常模式操作中操作第一触发器（L1）的第一触发器（L1）和第二触发器（L2）电源模式操作。缓冲电路电连接在第二触发器（L2）的扫出输出端和第一触发器（L1）的扫入输入端之间用于扫描链中的下一锁存器。缓冲电路控制元件控制第一触发器（L1）在扫描模式或低功耗模式之间切换。开关仅在一个时钟周期内发生。设计结构可以包括描述VLSI电路的网表，作为用于交换集成电路的布局数据的数据格式存储在存储介质上，并且优选地包括测试数据文件，表征数据，验证数据，或设计规格。

3. 发明申请

US20080177487A1 ESTIMATING STATIC POWER CONSUMPTION OF INTEGRATED CIRCUITS USING LOGIC GATE TEMPLATES 失效
标题翻译：使用逻辑门控模块估计集成电路的静态功耗
公开(公告)号：US20080177487A1
公开(公告)日：2008-07-24
申请号：US11626020
申请日：2007-01-23
申请人： Cedric Lichtenau , Alberto Garcia-Ortiz , Norman J. Rohrer
发明人： Cedric Lichtenau , Alberto Garcia-Ortiz , Norman J. Rohrer
IPC分类号： G01R21/00
CPC分类号： G01R31/2837
摘要： A method, system and computer program product for estimating a static power consumption of an integrated circuit are disclosed. The static power consumption of a cell of the integrated circuit is characterized based on contributions of an input node(s) and an output node(s) of the cell. A contribution considers a leakage weight and a leakage probability of a node. A logic template of the cell may be created to better represent a contribution of an internal node to the static power consumption of the cell.
摘要翻译：公开了一种用于估计集成电路的静态功耗的方法，系统和计算机程序产品。基于单元的输入节点和输出节点的贡献来表征集成电路的单元的静态功耗。贡献考虑了节点的泄漏重量和泄漏概率。可以创建小区的逻辑模板以更好地表示内部节点对小区的静态功耗的贡献。

4. 发明申请

US20090172615A1 METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION 有权
标题翻译：用于最小功率状态转换的方法和装置
公开(公告)号：US20090172615A1
公开(公告)日：2009-07-02
申请号：US11966493
申请日：2007-12-28
申请人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
发明人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/318536 , G01R31/318575 , G06F2217/14 , G06F2217/78
摘要： The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one clock cycle. The design structure can include a netlist, which describes the VLSI circuit, reside on storage medium as a data format used for the exchange of layout data of integrated circuits, and preferably includes at least one of test data files, characterization data, verification data, or design specifications.
摘要翻译：本发明包括体现在计算机可读介质中的设计结构，用于执行将扫描链插入到VLSI电路设计中的方法。扫描链结构或结构包含在VLSI电路设计的设计结构中。扫描链结构包括在扫描模式操作中，在初始化模式和低泄漏状态下，被配置为在正常模式操作中操作第一触发器（L1）的第一触发器（L1）和第二触发器（L2）电源模式操作。缓冲电路电连接在第二触发器（L2）的扫出输出端和第一触发器（L1）的扫入输入端之间用于扫描链中的下一锁存器。缓冲电路控制元件控制第一触发器（L1）在扫描模式或低功耗模式之间切换。开关仅在一个时钟周期内发生。设计结构可以包括描述VLSI电路的网表，作为用于交换集成电路的布局数据的数据格式存储在存储介质上，并且优选地包括测试数据文件，表征数据，验证数据，或设计规格。

5. 发明申请

US20080238494A1 METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION 失效
标题翻译：用于最小功率状态转换的方法和装置
公开(公告)号：US20080238494A1
公开(公告)日：2008-10-02
申请号：US11691856
申请日：2007-03-27
申请人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
发明人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
IPC分类号： H03B21/00
CPC分类号： G01R31/318541 , G01R31/318575
摘要： The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation. The switching occurs in only one clock cycle.
摘要翻译：本发明包括用于LSSD或GSD IC操作的新型扫描链结构。扫描链结构包括在扫描模式操作中在初始化模式下被配置为在正常模式操作中操作第一触发器（L1）的第一触发器（L 1）和第二触发器（L 2），以及在低泄漏功率模式操作中，其中锁存器的长扫描链内的每个触发器包括布置用于正常模式操作的数据输入，数据输出，时钟输入，扫描输入和扫描输出输出。缓冲电路电连接在扫描链中的下一个锁存器的第二触发器（L 2）的扫出输出和第一触发器（L1）的扫入输入端之间，缓冲电路包括控制元件，其控制第一触发器（L1）到扫描模式或低功率泄漏模式的操作。在从低功率泄漏模式退出时，第一触发器（L1）被设置为在正常模式操作期间初始化时被设置为相同值的数据输出值。开关仅在一个时钟周期内发生。

6. 发明授权

US07681153B2 Estimating static power consumption of integrated circuits using logic gate templates 失效
标题翻译：使用逻辑门模板估算集成电路的静态功耗
公开(公告)号：US07681153B2
公开(公告)日：2010-03-16
申请号：US11626020
申请日：2007-01-23
申请人： Cedric Lichtenau , Alberto Garcia-Ortiz , Norman J. Rohrer
发明人： Cedric Lichtenau , Alberto Garcia-Ortiz , Norman J. Rohrer
IPC分类号： G06F17/50
CPC分类号： G01R31/2837
摘要： A method, system and computer program product for estimating a static power consumption of an integrated circuit are disclosed. The static power consumption of a cell of the integrated circuit is characterized based on contributions of an input node(s) and an output node(s) of the cell. A contribution considers a leakage weight and a leakage probability of a node. A logic template of the cell may be created to better represent a contribution of an internal node to the static power consumption of the cell.
摘要翻译：公开了一种用于估计集成电路的静态功耗的方法，系统和计算机程序产品。基于单元的输入节点和输出节点的贡献来表征集成电路的单元的静态功耗。贡献考虑了节点的泄漏重量和泄漏概率。可以创建小区的逻辑模板以更好地表示内部节点对小区的静态功耗的贡献。

7. 发明申请

US20090021288A1 Signal Delay Element, Method and Integrated Circuit Device for Frequency Adjustment of Electronic Signals 有权
标题翻译：用于电子信号频率调整的信号延迟元件，方法和集成电路装置
公开(公告)号：US20090021288A1
公开(公告)日：2009-01-22
申请号：US12045894
申请日：2008-03-11
申请人： Florian Braun , Cedric Lichtenau , Thomas Pflueger , Ulrich Weiss
发明人： Florian Braun , Cedric Lichtenau , Thomas Pflueger , Ulrich Weiss
IPC分类号： H03B19/00
CPC分类号： H03K5/156 , H03K5/135 , H03K2005/00052 , H03L7/07 , H03L7/0814
摘要： The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.
摘要翻译：本发明涉及电子信号的频率调整。该方法包括以下步骤：提供具有第一频率的频率发生器的输出信号作为提供所述信号延迟元件的所述输入信号的边沿的信号延迟元件的输入信号; 通过向所述输入信号的每个周期添加延迟来延迟所述输入信号，直到信号延迟元件的延迟的输出信号与所述输入信号的边沿对准。

8. 发明授权

US07106110B2 Clock dithering system and method during frequency scaling 有权
标题翻译：时钟抖动系统和方法在频率缩放期间
公开(公告)号：US07106110B2
公开(公告)日：2006-09-12
申请号：US10710681
申请日：2004-07-28
申请人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
发明人： Miles G. Canada , Erwin B. Cohen , Jay G. Heaslip , Cedric Lichtenau , Thomas Pflueger , Mathew I. Ringler
IPC分类号： H03B19/00
CPC分类号： G06F1/08 , G06F1/324 , Y02D10/126
摘要： A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.
摘要翻译：一种将集成电路装置的时钟频率从第一频率转换到第二频率的系统和方法，包括根据抖动模式在第一频率和第二频率之间交替，交替发生预定数量的周期; 并且在预定次数的周期之后将时钟频率设置为第二频率。

9. 发明申请

US20050104637A1 SYSTEM AND METHOD FOR SYNCHRONIZING DIVIDE-BY COUNTERS 失效
标题翻译：同步计数器的系统和方法
公开(公告)号：US20050104637A1
公开(公告)日：2005-05-19
申请号：US10707066
申请日：2003-11-19
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
摘要翻译：能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

10. 发明授权

US07861129B2 Integrated circuit for writing and reading registers distributed across a semiconductor chip 失效
标题翻译：用于写入和读取分布在半导体芯片上的寄存器的集成电路
公开(公告)号：US07861129B2
公开(公告)日：2010-12-28
申请号：US12109529
申请日：2008-04-25
申请人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
发明人： Thuyen Le , Cedric Lichtenau , Martin Padeffke , Thomas Pflueger
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318555
摘要： An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a central control block. The integrated circuit comprises a plurality of circuit units. The circuit unit includes a functional portion with a local clock controller and one or more of the registers. The circuit unit includes a satellite portion. The central control block and the satellite portions are serially connected together and form a scan chain, wherein the scan chain is formed as a ring.
摘要翻译：一种半导体芯片上的集成电路，具有分布在半导体芯片上的多个寄存器。寄存器是可写和可读的。集成电路包括中央控制块。集成电路包括多个电路单元。电路单元包括具有本地时钟控制器和一个或多个寄存器的功能部分。电路单元包括卫星部分。中央控制块和卫星部分串联在一起并形成扫描链，其中扫描链形成为环。

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