专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120005516A1 SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM 有权
标题翻译：多节点计算机系统中的同步时钟停止
公开(公告)号：US20120005516A1
公开(公告)日：2012-01-05
申请号：US13170466
申请日：2011-06-28
申请人： Tobias BERGMANN , Ralf LUDEWIG , Tobias WEBEL , Ulrich WEISS
发明人： Tobias BERGMANN , Ralf LUDEWIG , Tobias WEBEL , Ulrich WEISS
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/3237 , Y02D10/128
摘要： A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.
摘要翻译：提供一种计算机系统，其包括多个节点，其包括不同类型的芯片。在每个节点中，一个芯片被配置为主芯片，其通过两个或更多个多点网络（例如，checkstop，clockrun）连接到一个或多个从芯片。主芯片和从芯片连接到参考时钟，事件触发信息通过多点网络（checkstop，clockrun）发送到从芯片。事件触发命令由主芯片在接收到请求时提交，内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。在运行中，偏移计数器由参考时钟同步。

2. 发明授权

US08086657B2 Adder structure with midcycle latch for power reduction 失效
标题翻译：加法器结构带有中间锁闩，用于降低功率
公开(公告)号：US08086657B2
公开(公告)日：2011-12-27
申请号：US12099973
申请日：2008-04-09
申请人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
发明人： Wilhelm Haller , Rolf Sautter , Christoph Wandel , Ulrich Weiss
IPC分类号： G06F7/50
CPC分类号： H03K19/0941 , H03K19/0008
摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.
摘要翻译：一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

3. 发明授权

US07761726B2 Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 失效
标题翻译：可扩展多处理器计算机中的容错时间同步机制的方法和装置
公开(公告)号：US07761726B2
公开(公告)日：2010-07-20
申请号：US12116652
申请日：2008-05-07
申请人： Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
发明人： Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译：冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。独立的步进同步信号被传送到几个同级芯片。本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。所有剩余的芯片都是从芯片。拓扑的所有段都是冗余的。多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

4. 发明授权

US07487377B2 Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 有权
标题翻译：可扩展多处理器计算机中的容错时间同步机制的方法和装置
公开(公告)号：US07487377B2
公开(公告)日：2009-02-03
申请号：US11054294
申请日：2005-02-09
申请人： Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
发明人： Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
IPC分类号： G06F13/42
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译：冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。独立的步进同步信号被传送到几个同级芯片。本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。所有剩余的芯片都是从芯片。拓扑的所有段都是冗余的。多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

5. 发明授权

US07296610B2 Method of manufacturing metallic components 失效
标题翻译：制造金属部件的方法
公开(公告)号：US07296610B2
公开(公告)日：2007-11-20
申请号：US10800544
申请日：2004-03-15
申请人： Matthew Zaluzec , David Cook , Ulrich Weiss , Maik Broda , Clemens Verpoort
发明人： Matthew Zaluzec , David Cook , Ulrich Weiss , Maik Broda , Clemens Verpoort
IPC分类号： B22D19/04 , B22D19/08
CPC分类号： B22D19/0009 , B22D19/0081 , B22D19/08 , C23C2/02 , C23C4/18 , C23C6/00 , F01L3/04 , F01L2101/00 , F01L2103/00 , Y10T29/49231 , Y10T29/49984
摘要： A method of manufacturing metallic components consisting of at least two different materials, one of them being an iron-based alloy and the other an aluminum-based alloy, and involving the steps of: depositing a metallic layer onto the body made from the iron-based alloy, said layer being an aluminum-based alloy, preferably based on Al—Si or Fe, placing the coated body in a casting mold and casting an aluminum-based alloy about the coated body. Prior to placing the body in the casting mold, the metallic layer of the body is sprayed and/or blasted with silicon powder and/or Borax (Na2B4O7—10H2O, hydrated sodium borate).
摘要翻译：一种制造由至少两种不同材料组成的金属组件的方法，其中一种是铁基合金，另一种是铝基合金，包括以下步骤：将金属层沉积在由铁 - 所述层是铝基合金，优选基于Al-Si或Fe，将涂覆体放置在铸模中并且在涂覆体周围浇铸铝基合金。在将本体放置在铸模中之前，用硅粉和/或硼砂（Na 2 B 4 O 4）喷射和/或喷射身体的金属层， N 2，水合硼酸钠）。

6. 发明申请

US20060179364A1 Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 有权
公开(公告)号：US20060179364A1
公开(公告)日：2006-08-10
申请号：US11054294
申请日：2005-02-09
申请人： Scott Swaney , Kenneth Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
发明人： Scott Swaney , Kenneth Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
IPC分类号： G06F11/00
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

7. 发明授权

US06989696B2 System and method for synchronizing divide-by counters 失效
标题翻译：用于同步分频计数器的系统和方法
公开(公告)号：US06989696B2
公开(公告)日：2006-01-24
申请号：US10707066
申请日：2003-11-19
申请人： Rolf Hilgendorf , Jens Kuenzer , Cédric Lichtenau , Thomas Pflueger , Mathew I. Ringler , Gerard M. Salem , Peter A. Sandon , Dana J. Thygesen , Ulrich Weiss
发明人： Rolf Hilgendorf , Jens Kuenzer , Cédric Lichtenau , Thomas Pflueger , Mathew I. Ringler , Gerard M. Salem , Peter A. Sandon , Dana J. Thygesen , Ulrich Weiss
IPC分类号： H03L7/00
CPC分类号： H03L7/06
摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
摘要翻译：能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

8. 发明授权

US4150236A Steroidal intermediates from the condensation product of dimethyl-3-ketoglutarate and glyoxal 失效
公开(公告)号：US4150236A
公开(公告)日：1979-04-17
申请号：US817094
申请日：1977-07-19
申请人： Ulrich Weiss , Kenner C. Rice
发明人： Ulrich Weiss , Kenner C. Rice
IPC分类号： C07C51/00 , C07C62/38 , C07C67/00 , C07C69/757 , C07C69/94
CPC分类号： C07C62/38
摘要： Tricyclic aromatic compounds of the formula ##STR1## including those wherein: (A) R.sub.1 is H, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(b) R.sub.1 is acetyl, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(c) R.sub.1 and R.sub.3 are methyl and R.sub.2 is carbomethoxy;(d) R.sub.1, R.sub.2, and R.sub.3 are hydrogen; and(e) R.sub.1 and R.sub.3 are methyl and R.sub.2 is hydrogenAre intermediates for the total synthesis of steroids.

9. 发明授权

US4139713A Steroidal intermediates from the condensation product of dimethyl-3-ketoglutarate and glyoxal 失效
公开(公告)号：US4139713A
公开(公告)日：1979-02-13
申请号：US817051
申请日：1977-07-19
申请人： Ulrich Weiss , Kenner C. Rice
发明人： Ulrich Weiss , Kenner C. Rice
IPC分类号： C07C51/00 , C07C62/38 , C07C67/00 , C07C69/757 , C07C69/95
CPC分类号： C07C62/38
摘要： Tricyclic aromatic compounds of the formula ##STR1## including those wherein: (A) R.sub.1 is H, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(b) R.sub.1 is acetyl, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(c) R.sub.1 and R.sub.3 are methyl and R.sub.2 is carbomethoxy;(d) R.sub.1, R.sub.2, and R.sub.3 are hydrogen; and(e) R.sub.1 and R.sub.3 are methyl and R.sub.2 is hydrogenAre intermediates for the total synthesis of steroids.

10. 发明申请

US20120117524A1 REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT 有权
标题翻译：可重复使用的结构硬件描述语言设计组件
公开(公告)号：US20120117524A1
公开(公告)日：2012-05-10
申请号：US12940762
申请日：2010-11-05
申请人： Friedhelm Kessler , Thomas M. Makowski , Harald Mielich , Ulrich Weiss
发明人： Friedhelm Kessler , Thomas M. Makowski , Harald Mielich , Ulrich Weiss
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.
摘要翻译：一种方法包括从硬件描述语言设计中移除代码段以创建修改的硬件描述语言设计。代码段表示硬件描述语言设计中至少一个时间敏感的路径。该方法包括创建经修改的硬件描述语言设计与在逻辑上等同于硬件描述语言设计的物理硬件表示之间的差异的增量列表。该方法包括至少部分地基于增量列表提取对应于时间敏感路径的物理硬件表示的一部分。该方法还包括使用所提取的物理硬件表示的部分来创建时间敏感路径的结构化硬件描述语言设计，其中所述结构化硬件描述语言设计包括所提取的所述物理硬件表示部分的结构信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式